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Rev Age Author Path Log message Diff
229 2665d 13h f9daq /cvi/RedPitaya/  
228 2670d 02h f9daq /cvi/instr/RedPitaya/ Red Pitaya socket server  
227 2670d 02h f9daq /cvi/instr/  
226 2670d 02h f9daq /cvi/  
225 2670d 02h f9daq /cvi/instr/RedPitaya/  
224 2673d 07h f9daq /cvi/instr/DRS/  
223 2690d 08h f9daq /cvi/instr/HISTO/  
222 2696d 16h f9daq /cvi/RedPitaya/ added export of the data to text, binary or root format.  
221 2698d 08h f9daq /cvi/instr/HISTO/  
220 2698d 09h f9daq /cvi/instr/HISTO/ set correct bin size  
219 2700d 12h f9daq /cvi/RedPitaya/  
218 2710d 22h f9daq /cvi/instr/AitSipmDAQ/data/ adcsum bug (double counting removed)  
217 2712d 07h f9daq /cvi/instr/DRS/  
216 2713d 09h f9daq /cvi/instr/AitSipmDAQ/data/  
215 2714d 05h f9daq /cvi/instr/AitSipmDAQ/data/  
214 2714d 05h f9daq /cvi/instr/AitSipmDAQ/  
213 2714d 05h f9daq /cvi/instr/AitSipmDAQ/AitSipmDAQDll/  
212 2714d 06h f9daq /cvi/instr/AitSipmDAQ/  
211 2716d 21h f9daq /cvi/RedPitaya/ RedPitaya SCPI DAQ  
210 2719d 12h f9daq /cvi/instr/DRS/ added stdio textwin  
209 2721d 07h f9daq /cvi/instr/HISTO/  
208 2721d 12h f9daq /drs/ creation of new output root file for each position point
adding the option to skip first n events		  
207 2726d 08h f9daq /cvi/instr/DRS/ change the output file format to the last version DRS2  
206 2726d 08h f9daq /drs/ bug in the position header removed  
205 2728d 08h f9daq /drs/ position record and star position record decoder changed  
204 2729d 12h f9daq /drs/ bug in the cftime calculation removed.
storage of the histograms in the root file added.		  
203 2736d 07h f9daq /cvi/instr/DRS/ MIKRO and scan added  
202 2736d 07h f9daq /drs/ posrec decoder added  
201 2739d 05h f9daq /cvi/instr/DRS/  
200 2739d 10h f9daq /cvi/instr/DRS/ plot of the waveforms extended  
199 2740d 11h f9daq /drs/  
198 2741d 06h f9daq /cvi/instr/ rename the project folder  
197 2741d 06h f9daq /cvi/instr/ rename the project folder  
196 2741d 06h f9daq /cvi/instr/drsctrl/ removed obj and exe files  
195 2741d 07h f9daq /cvi/instr/drsctrl/ DRS4 control  
194 2747d 06h f9daq /belle2/masterclass/ bug in the link removed  
193 2747d 06h f9daq /belle2/ Belle II masterclass  
192 2748d 06h f9daq /drs/  
191 2756d 12h f9daq /cvi/instr/  
190 2756d 12h f9daq /cvi/instr/CAENV462/