Subversion Repositories f9daq

control of the KEK PTS with the Wiener VME controller


<< PTS module specification >>

- Block diagram is shown in ptsblock.ps.gz (ptsblock.obj).
- The standard CPLD logic is assumed below.

[clock, NIM in/out selection in the CPLD]
   << CPLD logic >>
   (input)            (output)
   ICLK
   EXTCLK0_ --------> EXT[0]
   EXTCLK1_ --------> EXT[1]
   EXTCLK2_ --------> GCLK[2]
   EXTCLK3_ --------> GCLK[3]
   VOUT[0]            GCLK[0] = PCLK
   VOUT[1]            GCLK[1] = SCLK
   BUSA[0]            CLKOUT[0]
   BUSA[1]            CLKOUT[1]
   (internal)
   VMECLK

   - EXT[1:0], VOUT[1:0] are lines between the CPLD and FPGA.
   - BUSA[1:0] are lines connected to the connecter in the front panel.
   - VMECLK is an internal register.
   - CLKOUT[1:0] and GCLK[1:0] can be connected to any
     of input signals and VMECLK. This can be set by
     accessing ADR_CLK.

[VME addressed]
   A[31:12] must be selected by dip-switches.
   A[11:0]  is available in the module.
   A[11:0] = 12'b0000xxxxxxxx : reserved by CPLD (see pts_h.v)
             others           : available to FPGA

[Direction of BUS A-D]
   output = high(1'b1), input = low(1'b0)

[Pin assignment of BUS line]
   Front View
   +---------+
   | GND GND |
   | GND  15 |
   | GND  14 |
     .......
   | GND   1 |
   | GND   0 |
   +---------+





// pts_h.v
//
// 2000/09/09 ver 1.00  S.Nishida  (for ptscpld ver 1.00)
//

/* address */
`define ADR_CSR0    6'b000000
  // D[1]   LEDTEST
  // D[0]   RESET
`define ADR_CLK        6'b000001
  // D[15:12] CLKOUT1
  // D[11:8]  CLKOUT0
  // D[7:4]   SCLK
  // D[3:0]   PCLK
`define ADR_VMECLK    6'b000010
  // D[3]   CLKOUT1
  // D[2]   CLKOUT0
  // D[1]   SCLK
  // D[0]   PCLK
`define ADR_BUSA_REG    6'b000100
`define ADR_BUSA_IN    6'b000101
`define ADR_BUSA_DIR    6'b000110
  // D[1:0] BUSA direction
`define ADR_CFG        6'b010000
`define ADR_CSR1    6'b010001
  // D[8]   DONE
  // D[1]   VCS_
  // D[0]   PROGRAM_
`define ADR_MODE    6'b010010
`define ADR_SYSRESET    6'b111111
  // D[15:0] = 0x0000 is necessaly

/* BUSA direction */
`define DIRA_FPGA    2'b00
`define DIRA_IN        2'b10
`define DIRA_OUT    2'b11

/* CLK source */
`define CLK_IN        4'b0000
`define CLK_EXT0    4'b0001
`define CLK_EXT1    4'b0010
`define CLK_EXT2    4'b0011
`define CLK_EXT3    4'b0100
`define CLK_VME        4'b0101
`define CLK_VOUT0    4'b0110
`define CLK_VOUT1    4'b0111
`define CLK_BUSA0    4'b1000
`define CLK_BUSA1    4'b1001

/* Configuration Mode */
`define SELECTMAP_MODE        3'b010
`define SLAVESERIAL_MODE    3'b011