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  1. #ifndef __VIC_H__
  2. #define __VIC_H__
  3.  
  4. //****************************************************************************
  5. // Copyright (C) 2001-2004  ARW Elktronik Germany
  6. //
  7. // This program is free software; you can redistribute it and/or modify
  8. // it under the terms of the GNU General Public License as published by
  9. // the Free Software Foundation; either version 2 of the License, or
  10. // (at your option) any later version.
  11. //
  12. // This program is distributed in the hope that it will be useful,
  13. // but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15. // GNU General Public License for more details.
  16. //
  17. // You should have received a copy of the GNU General Public License
  18. // along with this program; if not, write to the Free Software
  19. // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. //
  21. // This product is not authorized for use as critical component in
  22. // life support systems without the express written approval of
  23. // ARW Elektronik Germany.
  24. //
  25. // Please announce changes and hints to ARW Elektronik
  26. //
  27. // Maintainer(s): Klaus Hitschler (klaus.hitschler@gmx.de)
  28. //****************************************************************************
  29.  
  30. //****************************************************************************
  31. //
  32. // vic.h - all definitions about the VIC68A chip
  33. //
  34. // $Log: vic.h,v $
  35. // Revision 1.6  2004/08/13 19:23:26  klaus
  36. // conversion to kernel-version 2.6, released version 3.0
  37. //
  38. // Revision 1.5  2002/10/18 21:56:28  klaus
  39. // completed functional features, untested
  40. //
  41. // Revision 1.4  2002/10/18 21:56:28  klaus
  42. // completed functional features, untested
  43. //
  44. // Revision 1.3  2002/10/10 18:57:46  klaus
  45. // source beautyfied
  46. //
  47. //****************************************************************************
  48.  
  49. //****************************************************************************
  50. // INCLUDES
  51. #include <linux/types.h>
  52.  
  53. //****************************************************************************
  54. // DEFINES
  55. #ifndef __KERNEL__
  56.     #define u8  __u8
  57.     #define u16 __u16
  58.     #define u32 __u32
  59. #endif
  60.  
  61. #define VICR1   (u16)0x07      /* VMEbus Interrupt Control Register #..  */
  62. #define VICR2   (u16)0x0b
  63. #define VICR3   (u16)0x0f  
  64. #define VICR4   (u16)0x13
  65. #define VICR5   (u16)0x17
  66. #define VICR6   (u16)0x1b
  67. #define VICR7   (u16)0x1f
  68.  
  69. #define LICR1   (u16)0x27      /* Local interrupt control register ..     */
  70. #define LICR2   (u16)0x2b
  71. #define LICR3   (u16)0x2f  
  72. #define LICR4   (u16)0x33
  73. #define LICR5   (u16)0x37
  74. #define LICR6   (u16)0x3b
  75. #define LICR7   (u16)0x3f
  76. #define LIVBR   (u16)0x57     /* Local interrupt vector base register     */
  77.  
  78. #define ICGSICR (u16)0x43     /* ICGS interrupt control register          */
  79. #define ICGSVBR (u16)0x4f     /* ICGS vector base register                */
  80.  
  81. #define ICMSICR (u16)0x47     /* ICMS interrupt control register          */
  82. #define ICMSVBR (u16)0x53     /* ICMS vector base register                */
  83.  
  84. #define EGICR   (u16)0x4b     /* Error group interrupt control register   */
  85. #define EGIVBR  (u16)0x5b     /* Error group interrupt vector base rg     */
  86.  
  87. #define ICSR    (u16)0x5f     /* Interprozessor communication switch rg   */
  88. #define ICR0    (u16)0x63
  89. #define ICR1    (u16)0x67
  90. #define ICR2    (u16)0x6b
  91. #define ICR3    (u16)0x6f
  92. #define ICR4    (u16)0x73
  93. #define ICR5    (u16)0x77
  94. #define ICR6    (u16)0x7b
  95. #define ICR7    (u16)0x7f
  96.  
  97. #define VIICR   (u16)0x03     /* VMEbus Interrupter Interrupt Control   */
  98. #define VIRSR   (u16)0x83     /* VMEbus interrupt request status reg    */
  99. #define VIVR1   (u16)0x87     /* VMEbus interrupt vector register ..    */
  100. #define VIVR2   (u16)0x8b
  101. #define VIVR3   (u16)0x8f
  102. #define VIVR4   (u16)0x93
  103. #define VIVR5   (u16)0x97
  104. #define VIVR6   (u16)0x9b
  105. #define VIVR7   (u16)0x9f
  106.  
  107. #define TTR     (u16)0xa3     /* transfer timeout register               */
  108. #define LTR     (u16)0xa7     /* local timing register                   */
  109. #define ICR     (u16)0xaf     /* interface configuration register        */
  110.  
  111. #define ARCR    (u16)0xb3     /* arbiter/requester configuration register*/
  112. #define AMSR    (u16)0xb7     /* address modifier source register        */
  113. #define BESR    (u16)0xbb     /* bus error source register               */
  114.  
  115. #define DSICR   (u16)0x23     /* DMA status interrupt control register   */
  116. #define DSR     (u16)0xbf     /* DMA status register                     */
  117.  
  118. #define SSCR00  (u16)0xc3     /* slave select 0 control register 0       */
  119. #define SSCR01  (u16)0xc7     /* slave select 0 control register 1       */
  120. #define SSCR10  (u16)0xcb     /* slave select 1 control register 0       */
  121. #define SSCR11  (u16)0xcf     /* slave select 1 control register 1       */
  122.  
  123. #define RCR     (u16)0xd3     /* release control register                */
  124.  
  125. #define BTDR    (u16)0xab     /* block transfer definition register      */
  126. #define BTCR    (u16)0xd7     /* block transfer control register         */
  127. #define BTLR0   (u16)0xdb     /* block transfer length register 0        */
  128. #define BTLR1   (u16)0xdf     /* block transfer length register 1        */
  129.  
  130. #define SRR     (u16)0xe3     /* system reset register                   */
  131.  
  132.  
  133. #endif // __VIC_H__
  134.  
  135.  
  136.