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  1. #ifndef __PLX9050_H__
  2. #define __PLX9050_H__
  3.  
  4. //****************************************************************************
  5. // Copyright (C) 2000-2004  ARW Elektronik Germany
  6. //
  7. //
  8. // This program is free software; you can redistribute it and/or modify
  9. // it under the terms of the GNU General Public License as published by
  10. // the Free Software Foundation; either version 2 of the License, or
  11. // (at your option) any later version.
  12. //
  13. // This program is distributed in the hope that it will be useful,
  14. // but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16. // GNU General Public License for more details.
  17. //
  18. // You should have received a copy of the GNU General Public License
  19. // along with this program; if not, write to the Free Software
  20. // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. //
  22. // This product is not authorized for use as critical component in
  23. // life support systems without the express written approval of
  24. // ARW Elektronik Germany.
  25. //  
  26. // Please announce changes and hints to ARW Elektronik
  27. //
  28. // Maintainer(s): Klaus Hitschler (klaus.hitschler@gmx.de)
  29. //
  30. //****************************************************************************
  31.  
  32. //****************************************************************************
  33. //
  34. // plx9050.h - Include header for the PCIbus target
  35. //             interface chip PLX9050 from PLX Technology (www.plxtech.com)
  36. //
  37. // $Log: plx9050.h,v $
  38. // Revision 1.6  2004/08/13 19:23:26  klaus
  39. // conversion to kernel-version 2.6, released version 3.0
  40. //
  41. // Revision 1.5  2002/10/18 21:56:28  klaus
  42. // completed functional features, untested
  43. //
  44. // Revision 1.4  2002/10/18 21:56:28  klaus
  45. // completed functional features, untested
  46. //
  47. // Revision 1.3  2002/10/10 18:57:46  klaus
  48. // source beautyfied
  49. //
  50. // derived from original code from Dirk Muehlenberg and ? Mathes   AR 18.02.2000
  51. //
  52. //****************************************************************************
  53.  
  54. #include <asm/io.h>
  55.  
  56. /*
  57.  * defining the offsets from PCI CFG Register Area
  58.  * (PCI registers, only accessible during a configuration 0 cycle)
  59.  */
  60. /* 15:0 VendorId | 31:16 DeviceId */
  61. #define PLX9050_PCIIDR   0x0
  62.  
  63. #define PLX9050_PCICR    0x4
  64. #define PLX9050_PCISR    0x6
  65. #define PLX9050_PCIREV   0x8
  66. #define PLX9050_PCICCR   0xB
  67. #define PLX9050_PCICLSR  0xC
  68. #define PLX9050_PCILTR   0xD
  69. #define PLX9050_PCIHTR   0xE
  70. #define PLX9050_PCIBISTR 0xF
  71. /*
  72. ** PCI Base Address Register
  73. */
  74. #define PLX9050_PCIBAR0  0x10
  75. #define PLX9050_PCIBAR1  0x14
  76. #define PLX9050_PCIBAR2  0x18
  77. #define PLX9050_PCIBAR3  0x1C
  78. #define PLX9050_PCIBAR4  0x20
  79. #define PLX9050_PCIBAR5  0x24
  80.  
  81. #define PLX9050_PCICIS   0x28
  82.  
  83. /* 15:0 Subsystem VendorId */
  84. #define PLX9050_PCISVID  0x2C
  85.  
  86. #define PLX9050_PCIERBAR 0x30
  87.  
  88. /* interrupt line routing */
  89. #define PLX9050_PCIILR   0x3C
  90. /* interrupt pin register */
  91. #define PLX9050_PCIIPR   0x3D
  92.  
  93. #define PLX9050_PCIMGR   0x3E
  94. #define PLX9050_PCIMLR   0x3F
  95.  
  96.  
  97. /*
  98.  * defining the offsets from Local Base Address
  99.  * (local configuration registers, accessible by way of i/o- or
  100.  * memory cycle)
  101.  */
  102. #define PLX9050_LAS0RR   0x0
  103. #define PLX9050_LAS1RR   0x4
  104. #define PLX9050_LAS2RR   0x8
  105. #define PLX9050_LAS3RR   0xC
  106. #define PLX9050_EROMRR   0x10
  107.  
  108. #define PLX9050_LAS0BA   0x14
  109. #define PLX9050_LAS1BA   0x18
  110. #define PLX9050_LAS2BA   0x1C
  111. #define PLX9050_LAS3BA   0x20
  112. #define PLX9050_EROMBA   0x24
  113.  
  114. /*
  115.  * Local Address Space I Bus Region Descriptor Register
  116.  * Bit
  117.  * 0 : Burst enable
  118.  * 1 : Ready Input Enable
  119.  * 2 : Bterm Input Enable
  120.  * 4:3 : Prefetch Count - 00 no, 01 4 lwords, 10 8 lwords, 11 16 lwords
  121.  * 5 : Prefetch Count Enable
  122.  */
  123. #define PLX9050_LAS0BRD  0x28
  124. #define PLX9050_LAS1BRD  0x2C
  125. #define PLX9050_LAS2BRD  0x30
  126. #define PLX9050_LAS3BRD  0x34
  127. #define PLX9050_EROMBRD  0x38
  128.  
  129. #define PLX9050_CS0BASE  0x3C
  130. #define PLX9050_CS1BASE  0x40
  131. #define PLX9050_CS2BASE  0x44
  132. #define PLX9050_CS4BASE  0x48
  133.  
  134. #define PLX9050_INTCSR   0x4C
  135.  
  136. #define PLX9050_CNTRL    0x50
  137.  
  138. #ifndef L_SETBIT
  139.     #define L_SETBIT(addr, b) writel(readl(addr) | (1<<(b)), addr);
  140.     #define W_SETBIT(addr, b) writew(readw(addr) | (1<<(b)), addr);
  141.     #define B_SETBIT(addr, b) writeb(readb(addr) | (1<<(b)), addr);
  142.  
  143.     #define L_CLRBIT(addr, b) writel(readl(addr) & ~(1<<(b)), addr);
  144.     #define W_CLRBIT(addr, b) writew(readw(addr) & ~(1<<(b)), addr);
  145.     #define B_CLRBIT(addr, b) writeb(readb(addr) & ~(1<<(b)), addr);
  146. #endif
  147.  
  148. #define PLX9050_ENABLE_BURST(base, i)  L_SETBIT(base+PLX9050_LAS0BRD+i*4, 0)
  149. #define PLX9050_DISABLE_BURST(base, i) L_CLRBIT(base+PLX9050_LAS0BRD+i*4, 0)
  150.  
  151. #define PLX9050_SET_PREFETCH0(base, i)  writel(readl(base+PLX9050_LAS0BRD+i*4) & ~0x180       , base+PLX9050_LAS0BRD+i*4);
  152. #define PLX9050_SET_PREFETCH4(base, i)  writel(readl(base+PLX9050_LAS0BRD+i*4) & ~0x180 | 0x80, base+PLX9050_LAS0BRD+i*4);
  153. #define PLX9050_SET_PREFETCH8(base, i)  writel(readl(base+PLX9050_LAS0BRD+i*4) & ~0x180 | 0x100, base+PLX9050_LAS0BRD+i*4);
  154. #define PLX9050_SET_PREFETCH16(base, i) writel(readl(base+PLX9050_LAS0BRD+i*4)          | 0x180, base+PLX9050_LAS0BRD+i*4);
  155.  
  156. #endif /* __PLX9050_H__ */
  157.