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-- Company:
-- Engineer:
--
-- Create Date: 12.10.2018 13:26:08
-- Design Name:
-- Module Name: dual_port_ram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dual_port_bram is
generic (
bit_num : natural := 10;
bin_num : natural := 1024; --number of histogram bins
buffer_size : natural := 10 -- buffer size in bits, 5 bit gets 32 different values
);
port (
-- A side --
clk_A: in std_logic;
bram_en_A: in std_logic;
wr_en_A: in std_logic;
addr_A: in unsigned ( (bit_num - 1) downto 0 );
data_in_A: in unsigned ( buffer_size downto 0 );
data_out_A: out unsigned ( buffer_size downto 0 );
-- B side --
clk_B: in std_logic;
bram_en_B: in std_logic;
wr_en_B: in std_logic;
addr_B: in unsigned ( (bit_num - 1) downto 0 );
data_in_B: in unsigned ( buffer_size downto 0 );
data_out_B: out unsigned ( buffer_size downto 0 )
);
end dual_port_bram;
architecture Behavioral of dual_port_bram is
type BRAM_ARRAY is array ( 0 to (bin_num - 1) ) of unsigned ( buffer_size downto 0 );
shared variable bram: BRAM_ARRAY := (others => (others => '0'));
begin
A_side: process (clk_A)
begin
if (rising_edge(clk_A)) then
if (bram_en_A = '1') then
if (wr_en_A = '1') then
bram(to_integer(addr_A)) := data_in_A;
end if;
data_out_A <= bram(to_integer(addr_A));
end if;
end if;
end process;
B_side: process (clk_B)
begin
if (rising_edge(clk_B)) then
if (bram_en_B = '1') then
if (wr_en_B = '1') then
bram(to_integer(addr_B)) := data_in_B;
end if;
data_out_B <= bram(to_integer(addr_B));
end if;
end if;
end process;
end Behavioral;