----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14.10.2018 11:13:46
-- Design Name:
-- Module Name: PE_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PE_unit is
generic (
bit_num : natural := 10; --number of data bits
bin_num : natural := 1024; --number of histogram bins
buffer_size : natural := 5; -- buffer size in bits, 5 bit gets 32 different values
byte: natural := 8;
mode: string := "MODE_3" -- modes of operation: MODE_1 = navaden algoritm, MODE_2 = odklop bufferja in 1 enota, MODE_3 = novo od 30.11.2018 naprej
);
port (
clk: in std_logic;
UC_wr_en: in std_logic; --microprocessor tells PE_unit that it read current data and is ready for the next one -- ustavljanje, poiljaj histogram takrat, ko je procesor ready, ne vsak clk cikel
PE_START: in std_logic; --flag that tells PE_unit that BRAM_buffer is full
data_in : in unsigned ( (bit_num - 1) downto 0 ); --data for PE unit from BRAM_buffer
BUFF_addr: out unsigned ( (buffer_size - 1) downto 0 ); -- address for BRAM_buffer, goes to PE_addr
PE_wr_rd_en: out std_logic; -- signal to tell BRAM_buffer to start sending when '1' and to tell PE_unit to start sending when '0'
data_out: out unsigned ( buffer_size downto 0 ); -- output data
UC_rd_en_final: out std_logic; --tells microprocessor that whole histogram data is ready to be sent from PE_unit to microprocessor
UC_rd_en_current: out std_logic; -- signal, ki procesorju omogoci sprotno branje iz brama2
---MODE_3 additional ports---
write_A_M3: in std_logic; --gre na write_A, ko smo v postopku branja,
ADC_unit_RESET: out std_logic;
PE_RESET: in std_logic
);
end PE_unit;
architecture Behavioral of PE_unit is
---------------------COMPONENTS-----------------------
component dual_port_bram is
generic (
bit_num : natural := 10;
bin_num : natural := 1024; --number of histogram bins
buffer_size : natural := 5 -- buffer size in bits, 5 bit gets 32 different values
);
port (
-- A side --
clk_A: in std_logic;
bram_en_A: in std_logic;
wr_en_A: in std_logic;
addr_A: in unsigned ( (bit_num - 1) downto 0 );
data_in_A: in unsigned ( buffer_size downto 0 );
data_out_A: out unsigned ( buffer_size downto 0 );
-- B side --
clk_B: in std_logic;
bram_en_B: in std_logic;
wr_en_B: in std_logic;
addr_B: in unsigned ( (bit_num - 1) downto 0 );
data_in_B: in unsigned ( buffer_size downto 0 );
data_out_B: out unsigned ( buffer_size downto 0 )
);
end component;
------------------SIGNALS-----------------------------
signal zeros : unsigned( buffer_size downto 0 ) := (others => '0'); --zero signal
signal zeros10: unsigned( (bit_num - 1) downto 0 ) := (others => '0');
signal old_value : unsigned ( (bit_num - 1) downto 0 );
signal new_value : unsigned ( (bit_num - 1) downto 0 );
signal BUFF_addr_sig : unsigned ( (buffer_size - 1) downto 0 ) := zeros(buffer_size - 1 downto 0); -- address for BRAM_buffer, goes to PE_addr
type state_type is (IDLE, WRITE, READ, RESET); --definicija avtomata s stirimi stanji
signal state: state_type := IDLE;
--values to be writen/read to/from bram1--
signal counter_new : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
signal counter_in : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
signal count_update : std_logic := '0';
signal start_counting : std_logic := '0';
signal bin_idx : unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
--signal bin_idx_reset : unsigned ( (bit_num - 1) downto 0 ) := (others => '0'); --this signal is address to write 0 into bram (to reset bram)
--bram1 control signals--
signal addr_A_sig : unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
signal addr_B_sig : unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
signal data_in_A_sig : unsigned ( buffer_size downto 0 ) := (others => '0');
signal data_out_B_sig : unsigned ( buffer_size downto 0 ) := (others => '0');
signal write_A: std_logic := '0';
signal read_B: std_logic := '0';
--other control signals --
signal PE_wr_rd_en_sig: std_logic := '0';
signal UC_rd_en_final_sig : std_logic := '0';
signal UC_rd_en_current_sig : std_logic := '0';
signal UC_wr_en_sig : std_logic := '0';
signal UC_wr_en_prev_sig: std_logic := '0';
signal delay_flag : boolean := FALSE; --used only to delay certain signals or states for 1 clock cycle
--MODE_3 signals--
signal RESET_sig: std_logic := '0'; --gledam rising edge reset signala, zato tudi reset_sig_prev signal
signal RESET_sig_prev: std_logic := '0';
signal ADC_unit_RESET_sig: std_logic := '0';
signal counter : unsigned ( (buffer_size ) downto 0 ) := (others =>'0'); --steje stevilo prejetih podatkov, ko pride do konca je buffer full
--bram2 signals
signal write_A_all_modes: std_logic := '0'; --izhod iz multiplekserja; ko sta MODE 1 in 2, je to stari write_A, drugace pa pulzni signal iz ADC_enote v MODE_3
signal write_A_prev_M3: std_logic := '0'; -- signal, s katerim gledam rising edge write_A_all_modes signala v MODE_3
signal data_out_bram1_sig : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
signal data_out_bram2_sig : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
signal read_B2: std_logic := '0';
signal addr_B2_sig : unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
signal data_out_sig : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
------------------FUNCTIONS-----------------------
function check_signal_edge( sig_in: std_logic;
sig_in_prev: std_logic;
type_of_edge: string) return boolean is --falling or rising
begin
if (type_of_edge = "rising") then
if (sig_in = '1' and sig_in_prev = '0') then
return TRUE;
else
return FALSE;
end if;
elsif (type_of_edge = "falling") then
if (sig_in = '0' and sig_in_prev = '1') then
return TRUE;
else
return FALSE;
end if;
end if;
end function;
----------------------------------------------------------------------------
begin
BRAM_connect: dual_port_bram generic map (bit_num => bit_num,
bin_num => bin_num,
buffer_size => buffer_size)
port map (clk_A => clk,
bram_en_A => write_A_all_modes, --spremenjeno 2.12.2018
wr_en_A => write_A_all_modes, -- -||-
addr_A => addr_A_sig,
data_in_A => data_in_A_sig,
data_out_A => open,
clk_B => clk,
bram_en_B => read_B,
wr_en_B => '0', --ni pisanja v B port, to more biti vedno onemogoèeno
addr_B => addr_B_sig,
data_in_B => zeros, --open ne pusti, zato sem dal zeros
data_out_B => data_out_B_sig );
-------------------------------------NALOGA BRAM_1-----------------------------------------------------
--stran A: a1) vpisovanje vrednosti iz BRAM_bufferja (preko algoritma za histogram) (state = WRITE)
-- a2) vpisovanje nicel (reset pomnilnika) (state = READ)
--stran B: b1) branje novega counterja (counter_new) za histogram algoritem (state = WRITE)
-- b2) branje izhodnih podatkov data_out (state = READ)
--HKRATI: a1) in b1)
-- a2) in b2)
------------------------------ COMB. DEL, KI VELJA ZA VSE MODE-e ------------------------------------------------------------
BUFF_addr <= BUFF_addr_sig;
PE_wr_rd_en <= PE_wr_rd_en_sig;
ADC_unit_RESET <= ADC_unit_RESET_sig;
new_value <= data_in when state = WRITE else
(others => '0');-- when state = READ or state = IDLE or state = RESET;
data_out <= data_out_sig;
--signals from/to microprocessor
UC_rd_en_final <= UC_rd_en_final_sig;
UC_rd_en_current <= UC_rd_en_current_sig;
UC_wr_en_sig <= UC_wr_en;
RESET_sig <= PE_RESET;
--------------------------------------------------------------------------------------------------------------------------------
--------------------------------MODE_1 AND MODE_2 ------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------
MODE_1_MODE_2: if (mode = "MODE_1" or mode = "MODE_2") generate
----------------------- COMBINATIONAL PART -----------------
---- Counter Adder----
counter_in <= (0 => '1', others => '0') when count_update = '0' else --mux - : tale enka tukaj zato, da ni 'X' na zacetku pr signalih, glej sliko v mapi slike, grafi itd.
(counter_new + 1) when count_update = '1'; --important part: this is where counter_new is increased every iteration
counter_new <= data_out_B_sig when state = WRITE else --demux
zeros;
----Data IN/OUT----
data_in_A_sig <= counter_in when state = WRITE else --mux
zeros when state = READ;
--TODO: dodaj se za RESET stanje (nicle)
data_out_sig <= data_out_B_sig when state = READ else -- demux
zeros;
---- Enable signals ----
write_A_all_modes <= write_A;
read_B <= PE_wr_rd_en_sig when state = WRITE else
not PE_wr_rd_en_sig when state = READ else
'0' when state = IDLE;
---- Address signals ----
addr_A_sig <= old_value when state = WRITE else
bin_idx - 1 when state = READ and bin_idx > 0 else
to_unsigned(bin_num - 1,10) when state = READ and delay_flag = TRUE else -- tukaj naj bo address 1023, da se vpise 0 na to mesto (reset)
zeros10 when state = IDLE;
addr_B_sig <= new_value when state = WRITE else
bin_idx when state = READ else
zeros10 when state = IDLE;
----------------------------------SEQUENTIAL PART -------------------------------------------
ALGORITHM: process(clk)
variable first_data: std_logic := '0';
begin
if rising_edge(clk) then
case state is
when IDLE =>
write_A <= '0'; -- this one is here, because we have to set it to '0' after program returns from READ state
--UC_rd_en_sig <= '0'; --ta tukej zato, da se v hist_system_top vpisejo vse vrednosti na data_out, pol pa sele tale dol pade
--writing condition--
if (PE_START = '1' and UC_rd_en_final_sig = '0' ) then -- and "konec posiljanja flag je ON" ) then -- sem pripravljen na sprejemanje
if(delay_flag = FALSE) then
delay_flag <= TRUE;
PE_wr_rd_en_sig <= '1'; --zacni sprejemanje
old_value <= zeros10;
BUFF_addr_sig <= zeros(buffer_size - 1 downto 0);
else
state <= WRITE;
delay_flag <= FALSE; -- ponastavitev delay flaga, da se lahko uporabi se drugje
old_value <= new_value;
BUFF_addr_sig <= BUFF_addr_sig + 1;
--first_data := '0'; --ponastavi, drugace se branje OK izvede samo prvic.
end if;
--reading condition, part 1 ---
elsif (PE_START = '0' and PE_wr_rd_en_sig = '1') then --sem pripravljen na poiljanje -- tole se lahko zgodi sele, ko gre najprej WRITE faza skozi,
PE_wr_rd_en_sig <= '0'; -- to pa zato, da od zacetka ne posilja nicel, ampak se vrti v IDLE stanju.
state <= READ;
--idle condition-----
else
state <= IDLE;
end if;
when WRITE =>
if (first_data = '0') then
first_data := '1';
old_value <= new_value;
BUFF_addr_sig <= BUFF_addr_sig + 1;
write_A <= '1';
start_counting <= '1';
else
if (write_A = '1') then
count_update <= '1';
else
count_update <= '0';
end if;
if (PE_START = '1') then
BUFF_addr_sig <= BUFF_addr_sig + 1;
elsif (PE_START = '0') then
BUFF_addr_sig <= (others =>'0'); --zeros(buffer_size - 1 downto 0);
delay_flag <= TRUE; -- s tem za en urin cikel zamaknem prehod v IDLE state in ponastavitev vsega, zato da se vsi podatki poracunajo
end if;
old_value <= new_value;
if (delay_flag = TRUE) then
delay_flag <= FALSE;
write_A <= '0';
count_update <= '0';
start_counting <= '0';
state <= IDLE;
first_data := '0'; --ponastavi, drugace se branje OK izvede samo prvic.
end if;
end if;
when READ => --za dodajanje procesorskega signala: signal vpliva samo na poveèevanje indeksov, ne na write in read in brama. samo ob pravem èasu more index poveèat
if (bin_idx = to_unsigned(2,bit_num) ) then --tole zato, da mi prvega podatka takoj ne pobrie, oz. da na 0, ampak ga ele potem, ko pride drugi podatek na izhodno vodilo : TODO: A NE BI MOGL BIT 1?? SPODEJ MAM 1 IN PROV DELA
write_A <= '1';
end if;
UC_rd_en_final_sig <= '1';
UC_wr_en_prev_sig <= UC_wr_en_sig; --ta signal zato, da lahko gledam falling edge od UC_wr_en, ker na falling edge menjam podatke: novo 15.11.2018
-------------------------------------------------------------
if (UC_wr_en_sig = '0' and UC_wr_en_prev_sig = '1') then -- ta pogoj je enak, kot da bi rekel if falling_edge (UC_wr_en)
bin_idx <= bin_idx + 1;
else
bin_idx <= bin_idx;
end if;
------------------------------------------------------------
if (bin_idx = bin_num - 1) then
--write_A <= '0';
bin_idx <= (others =>'0'); --zeros & "0000";
delay_flag <= TRUE;
end if;
if (delay_flag = TRUE) then
delay_flag <= FALSE;
state <= IDLE; --menjava stanj mora biti zakasnjena za 1 clk, da se se 1023 podatek vpise na data_out
UC_rd_en_final_sig <= '0';
end if;
end case;
end if;
end process;
end generate;
--------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-----------------------------MODE_3---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------
MODE_3: if (mode = "MODE_3") generate
--priklucitev dodatnega bufferja
BRAM_2_connect: dual_port_bram generic map (bit_num => bit_num,
bin_num => bin_num,
buffer_size => buffer_size)
port map (clk_A => clk,
bram_en_A => write_A_all_modes, --spremenjeno 2.12.2018
wr_en_A => write_A_all_modes, -- -||-
addr_A => addr_A_sig,
data_in_A => data_in_A_sig,
data_out_A => open,
clk_B => clk,
bram_en_B => read_B2,
wr_en_B => '0', --ni pisanja v B port, to more biti vedno onemogoèeno
addr_B => addr_B2_sig,
data_in_B => zeros,
data_out_B => data_out_bram2_sig );
--------COMBINATIONAL PART------------------
---- Counter Adder, BRAM_1----
counter_in <= (0 => '1', others => '0') when count_update = '0' else --mux - : tale enka tukaj zato, da ni 'X' na zacetku pr signalih, ker counter_new rab, da ga bram inicializira glej sliko v mapi slike, grafi itd.
(counter_new + 1) when count_update = '1'; --important part: this is where counter_new is increased every iteration
----Data IN/OUT, BRAM_1----
data_in_A_sig <= counter_in when state = WRITE else --mux
zeros;-- za vsa ostala stanja
data_out_bram1_sig <= data_out_B_sig when state = READ else -- demux
zeros;
counter_new <= data_out_B_sig when state = WRITE else --demux
zeros;
---- Enable signals, BRAM_1 ----
write_A_all_modes <= write_A_M3 when state = WRITE else
write_A when state = READ else --tukaj se vpisuejo nicle
'0' when state = IDLE else--v idle zdej pomoje lahko zbrises write_A = '0', preveri
'1' when state = RESET; --nicle vpisujes cel cajt, zato '1'
read_B <= PE_wr_rd_en_sig when state = WRITE else --TODO 31.3.2019: ali ni kar vseeno, da je addr_B_sig = '1', ko WR in RD in '0' else. <- ne, ker se pri WR stanju ta signal postavi z 1 clk zamude
not PE_wr_rd_en_sig when state = READ else
'0'; -- V stanjih IDLE in RESET
--TODO: 7.4.2019 PE_wr_rd_en_sig bom preimenoval v read_B_en (zaenkrat samo za na shematiko)!!!!!!!
---- Address signals, BRAM_1 ----
addr_A_sig <= old_value when state = WRITE else -- P2
bin_idx - 1 when state = READ and bin_idx > 0 else --P3
to_unsigned(bin_num - 1,10) when state = READ and delay_flag = TRUE else -- tukaj naj bo address 1023, da se vpise 0 na to mesto (reset) P4
(others =>'0') when state = IDLE else -- P1
bin_idx when state = RESET; --P5
addr_B_sig <= new_value when state = WRITE else
bin_idx when state = READ else
(others => '0'); --za ostali stanji IDLE in RESET
---- Data IN/OUT, BRAM_2 ----
--input v bram2 je kar data_in_A_sig prikljucen na input komponente bram2
--output bram2 je dat_out_bram2_sig , prikljuceno direktno na outB komponente bram2
---- Enable signals, BRAM_2 ----
--write_A_all_modes je tudi write enable signal bram2
read_B2 <= PE_wr_rd_en_sig when state = WRITE else
'1' when state = IDLE else --zato, da 1023. podatek pobrise iz data_out_bram2_sig
'0'; -- v stanjih READ IN RESET
--TODO: 7.4.2019 PE_wr_rd_en_sig bom preimenoval v read_B_en (zaenkrat samo za na shematiko)!!!!!!!
---- Address signals, BRAM_2 ----
--addr_A_sig : za vpisovanje je enak naslov kot pri bram1
addr_B2_sig <= bin_idx when state = WRITE else
(others => '0'); -- v stanjih READ, IDLE IN RESET
--------skupna logika obeh bram-ov---------------------
data_out_sig <= data_out_bram2_sig when state = WRITE else
data_out_bram1_sig when state = READ else
(others => '0'); --pri IDLE in RESET stanju
--------SEQUENTIAL PART---------------------
ALGORITHM_bram_1: process(clk)
variable first_data: std_logic := '0';
variable buffer_full: std_logic := '0'; -- 0 - ni se poln, 1 - bram je poln
begin
if rising_edge(clk) then
case state is
when IDLE =>
if (PE_START = '1') then --START SIGNAL
write_A <= '0'; -- this one is here, because we have to set it to '0' after program returns from READ state
if (buffer_full = '0' and RESET_sig = '0') then -- ni se cas za posiljanje, se pravi lahko sprejemam --PISANJE V PE ENOTO
PE_wr_rd_en_sig <= '1'; --tole vezano na read_B, zato ga se vedno obdrzim
old_value <= (others => '0');
state <= WRITE;
--old_value <= new_value;
elsif (buffer_full = '1' and RESET_sig = '0') then --BRANJE NA KONCU IZ PE ENOTE
--pisi na vodilo na koncu in resetiraj prvi bram, tako kot do sedaj, skratka pojdi v READ stanje
bin_idx <= (others => '0'); --ga resetiram, da je 0, ker ga tudi bram 2 uproablja
UC_wr_en_prev_sig <= '0'; -- da ga ponastavim, ker drugace mi 0. podatek takoj preklopi v 1., ne caka na falling edge od UC_wr_en_sig
state <= READ;
elsif (check_signal_edge(RESET_sig,RESET_sig_prev,"rising")) then
state <= RESET;
ADC_unit_RESET_sig <= '1';
end if;
elsif (PE_START = '0') then --CE JE START NA '0'
if (check_signal_edge(RESET_sig,RESET_sig_prev,"rising")) then
state <= RESET;
bin_idx <= (others => '0');
ADC_unit_RESET_sig <= '1';
else
state <= IDLE;
end if;
end if;
--stimanje reset signala
RESET_sig_prev <= RESET_sig;
----------------------------
when WRITE =>
-------------------bram_1 handling---------------------
old_value <= new_value;
count_update <= '1'; --ta tukaj samo zato, da nimam 'X' v simulaciji, glej sliko v mapi slike_grafi itd.
write_A_prev_M3 <= write_A_all_modes;
if (write_A_all_modes = '1' and write_A_prev_M3 = '0') then --rising edge write signala
counter <= counter + 1;
end if;
if (counter = 2**buffer_size) then --ko sem prejel maksimalno t. podatkov, ki jih lahko buffer shrani TODO: 18.5.2019: PREVERI TUKEJ, CE JE counter_in = 2*buffer_size -1
--kok delaya? -- nc ni treba
state <= IDLE;
buffer_full := '1';
PE_wr_rd_en_sig <= '0';
count_update <= '0';
counter <= (others => '0');
end if;
-----------------bram_2 handling ----------------------
if (counter > 0 and counter < 2**buffer_size) then --ce si ze vpisal vsaj en podatek in se nisi prisel do konca vpisovanja
UC_rd_en_current_sig <= '1'; --povej procesorju, da lahko zacne sprotno branje
elsif (counter = 2**buffer_size) then
UC_rd_en_current_sig <= '0'; -- procesor naj konca sprotno branje
end if;
UC_wr_en_prev_sig <= UC_wr_en_sig; --ta signal zato, da lahko gledam falling edge od UC_wr_en, ker na falling edge menjam podatke:
if (UC_rd_en_current_sig = '1') then --ce je omogoceno sprotno branje, lahko podajas podatke na izhod
if (check_signal_edge(UC_wr_en_sig, UC_wr_en_prev_sig, "falling")) then -- ta pogoj je enak, kot da bi rekel if falling_edge (UC_wr_en)
bin_idx <= bin_idx + 1;
else
bin_idx <= bin_idx;
end if;
end if;
-- if (bin_idx = bin_num - 1) then
-- --bin_idx <= (others =>'0'); --zeros & "0000";
-- delay_flag <= TRUE;
-- end if;
-- if (delay_flag = TRUE) then
-- delay_flag <= FALSE;
-- --UC_wr_en_prev_sig <= '0';
-- --bin_idx <= (others => '0');
-- end if;
--------------------RESET handling--------------------------
RESET_sig_prev <= RESET_sig;
if (check_signal_edge(RESET_sig,RESET_sig_prev,"rising")) then
state <= RESET;
bin_idx <= (others =>'0');
UC_rd_en_current_sig <= '0';
ADC_unit_RESET_sig <= '1';
end if;
-----------------STOP SYSTEM handling ------------------------
if (PE_START = '0') then
state <= IDLE;
UC_rd_en_current_sig <= '0';
end if;
when READ => --za dodajanje procesorskega signala: signal vpliva samo na poveèevanje indeksov, ne na write in read in brama. samo ob pravem èasu more index poveèat
UC_rd_en_final_sig <= '1';
-------------------------------------------------------------
UC_wr_en_prev_sig <= UC_wr_en_sig; --ta signal zato, da lahko gledam falling edge od UC_wr_en, ker na falling edge menjam podatke: novo 15.11.2018
if (UC_rd_en_final_sig = '1') then --to zato, da, ce se ponesreci vrine kaksen UC_wr_en preden skoci UC_rd_en_final na '1', da se nic ne zgodi
if ( check_signal_edge(UC_wr_en_sig, UC_wr_en_prev_sig, "falling") ) then -- ta pogoj je enak, kot da bi rekel if falling_edge (UC_wr_en)
bin_idx <= bin_idx + 1;
else
bin_idx <= bin_idx;
end if;
end if;
------------------------------------------------------------
if (bin_idx = to_unsigned(1,bit_num) ) then --tole zato, da mi prvega podatka takoj ne pobrie, oz. da na 0, ampak ga ele potem, ko pride drugi podatek na izhodno vodilo
write_A <= '1';
end if;
if (bin_idx = bin_num - 1) then
bin_idx <= (others =>'0');
delay_flag <= TRUE;
end if;
if (delay_flag = TRUE) then
delay_flag <= FALSE;
state <= IDLE; --menjava stanj mora biti zakasnjena za 1 clk, da se se 1023 podatek vpise na data_out
UC_rd_en_final_sig <= '0';
bin_idx <= (others => '0'); --se enkrat na 0, drugace se zaradi delaya spet postavi na 1
buffer_full := '0';
end if;
--------------------RESET handling--------------------------
RESET_sig_prev <= RESET_sig;
if (check_signal_edge(RESET_sig,RESET_sig_prev,"rising")) then
state <= RESET;
bin_idx <= (others => '0');
UC_rd_en_final_sig <= '0';
ADC_unit_RESET_sig <= '1';
end if;
-----------------STOP SYSTEM handling ------------------------
if (PE_START = '0') then
state <= IDLE;
UC_rd_en_final_sig <= '0'; --ce gres tkole: READ -> IDLE -> RESET, potem je treba tega tuki ugasnt
end if;
when RESET =>
bin_idx <= bin_idx + 1; --to je naslov, v katerega se v oba bram-a vpisujejo nicle
if (bin_idx = bin_num - 1) then
bin_idx <= (others => '0');
state <= IDLE;
ADC_unit_RESET_sig <= '0';
end if;
PE_wr_rd_en_sig <= '0';
count_update <= '0';
counter <= (others => '0');
buffer_full := '0';
end case;
end if;
end process;
end generate;
end Behavioral;