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#ifndef __VIC_H__
#define __VIC_H__
//------------------------------------------------------------------------------------------
// vic.h - some constants about the VIC68A chip from cypress semiconductor
//
// (c) 1999-2004 ARW Elektronik
//
// this source code is published under GPL (Open Source). You can use, redistrubute and
// modify it unless this header is not modified or deleted. No warranty is given that
// this software will work like expected.
// This product is not authorized for use as critical component in life support systems
// wihout the express written approval of ARW Elektronik Germany.
//
// Please announce changes and hints to ARW Elektronik
//
//
// $Log: Vic.h,v $
// Revision 1.3 2004/07/24 07:07:26 klaus
// Update copyright to 2004
//
// Revision 1.2 2003/11/15 19:12:51 klaus
// Update copyright to 2003
//
// Revision 1.1.1.1 2003/11/14 23:16:33 klaus
// First put into repository
//
// Revision 1.3 2002/10/27 16:17:48 klaus
// Typing bug fixed caused at log addition
//
// Revision 1.2 2002/10/27 16:11:03 klaus
// Added CVS log into header
//
// what who when
// finished first release to use with the PCIVME interface of ARW AR 24.11.1997
// SRR corrected from SSR AR 18.04.1999
//
/* all address offsets relative to vic base */
#define VICR1 (WORD)0x07 /* VMEbus Interrupt Control Register #.. */
#define VICR2 (WORD)0x0b
#define VICR3 (WORD)0x0f
#define VICR4 (WORD)0x13
#define VICR5 (WORD)0x17
#define VICR6 (WORD)0x1b
#define VICR7 (WORD)0x1f
#define LICR1 (WORD)0x27 /* Local interrupt control register .. */
#define LICR2 (WORD)0x2b
#define LICR3 (WORD)0x2f
#define LICR4 (WORD)0x33
#define LICR5 (WORD)0x37
#define LICR6 (WORD)0x3b
#define LICR7 (WORD)0x3f
#define LIVBR (WORD)0x57 /* Local interrupt vector base register */
#define ICGSICR (WORD)0x43 /* ICGS interrupt control register */
#define ICGSVBR (WORD)0x4f /* ICGS vector base register */
#define ICMSICR (WORD)0x47 /* ICMS interrupt control register */
#define ICMSVBR (WORD)0x53 /* ICMS vector base register */
#define EGICR (WORD)0x4b /* Error group interrupt control register */
#define EGIVBR (WORD)0x5b /* Error group interrupt vector base rg */
#define ICSR (WORD)0x5f /* Interprozessor communication switch rg */
#define ICR0 (WORD)0x63
#define ICR1 (WORD)0x67
#define ICR2 (WORD)0x6b
#define ICR3 (WORD)0x6f
#define ICR4 (WORD)0x73
#define ICR5 (WORD)0x77
#define ICR6 (WORD)0x7b
#define ICR7 (WORD)0x7f
#define VIICR (WORD)0x03 /* VMEbus Interrupter Interrupt Control */
#define VIRSR (WORD)0x83 /* VMEbus interrupt request status reg */
#define VIVR1 (WORD)0x87 /* VMEbus interrupt vector register .. */
#define VIVR2 (WORD)0x8b
#define VIVR3 (WORD)0x8f
#define VIVR4 (WORD)0x93
#define VIVR5 (WORD)0x97
#define VIVR6 (WORD)0x9b
#define VIVR7 (WORD)0x9f
#define TTR (WORD)0xa3 /* transfer timeout register */
#define LTR (WORD)0xa7 /* local timing register */
#define ICR (WORD)0xaf /* interface configuration register */
#define ARCR (WORD)0xb3 /* arbiter/requester configuration register*/
#define AMSR (WORD)0xb7 /* address modifier source register */
#define BESR (WORD)0xbb /* bus error source register */
#define DSICR (WORD)0x23 /* DMA status interrupt control register */
#define DSR (WORD)0xbf /* DMA status register */
#define SSCR00 (WORD)0xc3 /* slave select 0 control register 0 */
#define SSCR01 (WORD)0xc7 /* slave select 0 control register 1 */
#define SSCR10 (WORD)0xcb /* slave select 1 control register 0 */
#define SSCR11 (WORD)0xcf /* slave select 1 control register 1 */
#define RCR (WORD)0xd3 /* release control register */
#define BTDR (WORD)0xab /* block transfer definition register */
#define BTCR (WORD)0xd7 /* block transfer control register */
#define BTLR0 (WORD)0xdb /* block transfer length register 0 */
#define BTLR1 (WORD)0xdf /* block transfer length register 1 */
#define SRR (WORD)0xe3 /* system reset register */
#endif
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------