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  1. #ifndef __PLX9050_H__
  2. #define __PLX9050_H__
  3.  
  4. //****************************************************************************
  5. // Copyright (C) 2000-2004  ARW Elektronik Germany
  6. //
  7. //
  8. // This program is free software; you can redistribute it and/or modify
  9. // it under the terms of the GNU General Public License as published by
  10. // the Free Software Foundation; either version 2 of the License, or
  11. // (at your option) any later version.
  12. //
  13. // This program is distributed in the hope that it will be useful,
  14. // but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16. // GNU General Public License for more details.
  17. //
  18. // You should have received a copy of the GNU General Public License
  19. // along with this program; if not, write to the Free Software
  20. // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. //
  22. // This product is not authorized for use as critical component in
  23. // life support systems without the express written approval of
  24. // ARW Elektronik Germany.
  25. //  
  26. // Please announce changes and hints to ARW Elektronik
  27. //
  28. // Maintainer(s): Klaus Hitschler (klaus.hitschler@gmx.de)
  29. //
  30. //****************************************************************************
  31.  
  32. //****************************************************************************
  33. //
  34. // plx9050.h - Include header for the PCIbus target
  35. //             interface chip PLX9050 from PLX Technology (www.plxtech.com)
  36. //
  37. // $Log: plx9050.h,v $
  38. // Revision 1.3  2004/08/12 19:59:19  klaus
  39. // conversion to kernel-version 2.6, released version 6.0
  40. //
  41. // Revision 1.2  2001/11/20 20:12:50  klaus
  42. // included new header and CVS log
  43. //
  44. //
  45. // derived from original code from Dirk Muehlenberg and ? Mathes   AR 18.02.2000
  46. //
  47. //****************************************************************************
  48.  
  49. #include <asm/io.h>
  50.  
  51. /*
  52.  * defining the offsets from PCI CFG Register Area
  53.  * (PCI registers, only accessible during a configuration 0 cycle)
  54.  */
  55. /* 15:0 VendorId | 31:16 DeviceId */
  56. #define PLX9050_PCIIDR   0x0
  57.  
  58. #define PLX9050_PCICR    0x4
  59. #define PLX9050_PCISR    0x6
  60. #define PLX9050_PCIREV   0x8
  61. #define PLX9050_PCICCR   0xB
  62. #define PLX9050_PCICLSR  0xC
  63. #define PLX9050_PCILTR   0xD
  64. #define PLX9050_PCIHTR   0xE
  65. #define PLX9050_PCIBISTR 0xF
  66. /*
  67. ** PCI Base Address Register
  68. */
  69. #define PLX9050_PCIBAR0  0x10
  70. #define PLX9050_PCIBAR1  0x14
  71. #define PLX9050_PCIBAR2  0x18
  72. #define PLX9050_PCIBAR3  0x1C
  73. #define PLX9050_PCIBAR4  0x20
  74. #define PLX9050_PCIBAR5  0x24
  75.  
  76. #define PLX9050_PCICIS   0x28
  77.  
  78. /* 15:0 Subsystem VendorId */
  79. #define PLX9050_PCISVID  0x2C
  80.  
  81. #define PLX9050_PCIERBAR 0x30
  82.  
  83. /* interrupt line routing */
  84. #define PLX9050_PCIILR   0x3C
  85. /* interrupt pin register */
  86. #define PLX9050_PCIIPR   0x3D
  87.  
  88. #define PLX9050_PCIMGR   0x3E
  89. #define PLX9050_PCIMLR   0x3F
  90.  
  91.  
  92. /*
  93.  * defining the offsets from Local Base Address
  94.  * (local configuration registers, accessible by way of i/o- or
  95.  * memory cycle)
  96.  */
  97. #define PLX9050_LAS0RR   0x0
  98. #define PLX9050_LAS1RR   0x4
  99. #define PLX9050_LAS2RR   0x8
  100. #define PLX9050_LAS3RR   0xC
  101. #define PLX9050_EROMRR   0x10
  102.  
  103. #define PLX9050_LAS0BA   0x14
  104. #define PLX9050_LAS1BA   0x18
  105. #define PLX9050_LAS2BA   0x1C
  106. #define PLX9050_LAS3BA   0x20
  107. #define PLX9050_EROMBA   0x24
  108.  
  109. /*
  110.  * Local Address Space I Bus Region Descriptor Register
  111.  * Bit
  112.  * 0 : Burst enable
  113.  * 1 : Ready Input Enable
  114.  * 2 : Bterm Input Enable
  115.  * 4:3 : Prefetch Count - 00 no, 01 4 lwords, 10 8 lwords, 11 16 lwords
  116.  * 5 : Prefetch Count Enable
  117.  */
  118. #define PLX9050_LAS0BRD  0x28
  119. #define PLX9050_LAS1BRD  0x2C
  120. #define PLX9050_LAS2BRD  0x30
  121. #define PLX9050_LAS3BRD  0x34
  122. #define PLX9050_EROMBRD  0x38
  123.  
  124. #define PLX9050_CS0BASE  0x3C
  125. #define PLX9050_CS1BASE  0x40
  126. #define PLX9050_CS2BASE  0x44
  127. #define PLX9050_CS4BASE  0x48
  128.  
  129. #define PLX9050_INTCSR   0x4C
  130.  
  131. #define PLX9050_CNTRL    0x50
  132.  
  133. #ifndef L_SETBIT
  134. #define L_SETBIT(addr, b) writel(readl(addr) | (1<<(b)), addr);
  135. #define W_SETBIT(addr, b) writew(readw(addr) | (1<<(b)), addr);
  136. #define B_SETBIT(addr, b) writeb(readb(addr) | (1<<(b)), addr);
  137.  
  138. #define L_CLRBIT(addr, b) writel(readl(addr) & ~(1<<(b)), addr);
  139. #define W_CLRBIT(addr, b) writew(readw(addr) & ~(1<<(b)), addr);
  140. #define B_CLRBIT(addr, b) writeb(readb(addr) & ~(1<<(b)), addr);
  141. #endif
  142.  
  143. #define PLX9050_ENABLE_BURST(base, i)  L_SETBIT(base+PLX9050_LAS0BRD+i*4, 0)
  144. #define PLX9050_DISABLE_BURST(base, i) L_CLRBIT(base+PLX9050_LAS0BRD+i*4, 0)
  145.  
  146. #define PLX9050_SET_PREFETCH0(base, i)  writel(readl(base+PLX9050_LAS0BRD+i*4) & ~0x180       , base+PLX9050_LAS0BRD+i*4);
  147. #define PLX9050_SET_PREFETCH4(base, i)  writel(readl(base+PLX9050_LAS0BRD+i*4) & ~0x180 | 0x80, base+PLX9050_LAS0BRD+i*4);
  148. #define PLX9050_SET_PREFETCH8(base, i)  writel(readl(base+PLX9050_LAS0BRD+i*4) & ~0x180 | 0x100, base+PLX9050_LAS0BRD+i*4);
  149. #define PLX9050_SET_PREFETCH16(base, i) writel(readl(base+PLX9050_LAS0BRD+i*4)          | 0x180, base+PLX9050_LAS0BRD+i*4);
  150.  
  151. #endif /* __PLX9050_H__ */
  152.