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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /lab @ 181

  → /lab/ @ 336

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 181 → Rev 336

/lab/izolirana_perfuzija_udov/GUI/GUI_2.mlapp
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Index: izolirana_perfuzija_udov/Hardware/Libraries/74HC/74HC.PCBLIB
===================================================================
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svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/74HC/74HC.PCBLIB
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Added: svn:mime-type
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Index: izolirana_perfuzija_udov/Hardware/Libraries/74HC/74HC.SchLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/74HC/74HC.SchLib
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Index: izolirana_perfuzija_udov/Hardware/Libraries/74HC.IntLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/74HC.IntLib
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Index: izolirana_perfuzija_udov/Hardware/Libraries/AVR.IntLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/AVR.IntLib
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Index: izolirana_perfuzija_udov/Hardware/Libraries/DAQ_REV_B.IntLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/DAQ_REV_B.IntLib
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Added: svn:mime-type
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Index: izolirana_perfuzija_udov/Hardware/Libraries/Displays.IntLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/Displays.IntLib
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Index: izolirana_perfuzija_udov/Hardware/Libraries/FTDI.IntLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/FTDI.IntLib
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Index: izolirana_perfuzija_udov/Hardware/Libraries/General/General.PCBLIB
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/General/General.PCBLIB
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Added: svn:mime-type
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Index: izolirana_perfuzija_udov/Hardware/Libraries/General/General.SchLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/General/General.SchLib
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Index: izolirana_perfuzija_udov/Hardware/Libraries/General/History/General.~(1).PCBLIB.Zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/General/History/General.~(1).PCBLIB.Zip
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Index: izolirana_perfuzija_udov/Hardware/Libraries/General/History/General.~(1).SchLib.Zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/General/History/General.~(1).SchLib.Zip
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Index: izolirana_perfuzija_udov/Hardware/Libraries/General/History/General.~(2).PCBLIB.Zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/General/History/General.~(2).PCBLIB.Zip
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Index: izolirana_perfuzija_udov/Hardware/Libraries/General/History/General.~(2).SchLib.Zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/General/History/General.~(2).SchLib.Zip
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Index: izolirana_perfuzija_udov/Hardware/Libraries/General.IntLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/General.IntLib
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Index: izolirana_perfuzija_udov/Hardware/Libraries/ICgeneral.IntLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/ICgeneral.IntLib
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Index: izolirana_perfuzija_udov/Hardware/Libraries/Kon_Tipk.IntLib
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

/izolirana_perfuzija_udov/Hardware/Libraries/Kon_Tipk.IntLib
Property changes:
Added: svn:mime-type
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Index: izolirana_perfuzija_udov/Hardware/Libraries/Kon_Tipk_1.LibPkg
===================================================================
--- izolirana_perfuzija_udov/Hardware/Libraries/Kon_Tipk_1.LibPkg (nonexistent)
+++ izolirana_perfuzija_udov/Hardware/Libraries/Kon_Tipk_1.LibPkg (revision 336)
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+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=BOM_PartType
+OutputName1=Bill of Materials
+OutputDocumentPath1=
+OutputVariantName1=[No Variations]
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=ComponentCrossReference
+OutputName2=Component Cross Reference Report
+OutputDocumentPath2=
+OutputVariantName2=[No Variations]
+OutputDefault2=0
+OutputType3=ReportHierarchy
+OutputName3=Report Project Hierarchy
+OutputDocumentPath3=
+OutputVariantName3=[No Variations]
+OutputDefault3=0
+OutputType4=Script
+OutputName4=Script Output
+OutputDocumentPath4=
+OutputVariantName4=[No Variations]
+OutputDefault4=0
+OutputType5=SimpleBOM
+OutputName5=Simple BOM
+OutputDocumentPath5=
+OutputVariantName5=[No Variations]
+OutputDefault5=0
+OutputType6=SinglePinNetReporter
+OutputName6=Report Single Pin Nets
+OutputDocumentPath6=
+OutputVariantName6=[No Variations]
+OutputDefault6=0
+
+[OutputGroup7]
+Name=Other Outputs
+Description=
+TargetPrinter=HP Deskjet 4620 series (Network)
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Text Print
+OutputName1=Text Print
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=Text Print
+OutputName2=Text Print
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType3=Text Print
+OutputName3=Text Print
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType4=Text Print
+OutputName4=Text Print
+OutputDocumentPath4=
+OutputVariantName4=
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=Text Print
+OutputName5=Text Print
+OutputDocumentPath5=
+OutputVariantName5=
+OutputDefault5=0
+PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType6=Text Print
+OutputName6=Text Print
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType7=Text Print
+OutputName7=Text Print
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType8=Text Print
+OutputName8=Text Print
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType9=Text Print
+OutputName9=Text Print
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType10=Text Print
+OutputName10=Text Print
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType11=Text Print
+OutputName11=Text Print
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType12=Text Print
+OutputName12=Text Print
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType13=Text Print
+OutputName13=Text Print
+OutputDocumentPath13=
+OutputVariantName13=
+OutputDefault13=0
+PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType14=Text Print
+OutputName14=Text Print
+OutputDocumentPath14=
+OutputVariantName14=
+OutputDefault14=0
+PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType15=Text Print
+OutputName15=Text Print
+OutputDocumentPath15=
+OutputVariantName15=
+OutputDefault15=0
+PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType16=Text Print
+OutputName16=Text Print
+OutputDocumentPath16=
+OutputVariantName16=
+OutputDefault16=0
+PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType17=Text Print
+OutputName17=Text Print
+OutputDocumentPath17=
+OutputVariantName17=
+OutputDefault17=0
+PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType18=Text Print
+OutputName18=Text Print
+OutputDocumentPath18=
+OutputVariantName18=
+OutputDefault18=0
+PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType19=Text Print
+OutputName19=Text Print
+OutputDocumentPath19=
+OutputVariantName19=
+OutputDefault19=0
+PageOptions19=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType20=Text Print
+OutputName20=Text Print
+OutputDocumentPath20=
+OutputVariantName20=
+OutputDefault20=0
+PageOptions20=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType21=Text Print
+OutputName21=Text Print
+OutputDocumentPath21=
+OutputVariantName21=
+OutputDefault21=0
+PageOptions21=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType22=Text Print
+OutputName22=Text Print
+OutputDocumentPath22=
+OutputVariantName22=
+OutputDefault22=0
+PageOptions22=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType23=Text Print
+OutputName23=Text Print
+OutputDocumentPath23=
+OutputVariantName23=
+OutputDefault23=0
+PageOptions23=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType24=Text Print
+OutputName24=Text Print
+OutputDocumentPath24=
+OutputVariantName24=
+OutputDefault24=0
+PageOptions24=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType25=Text Print
+OutputName25=Text Print
+OutputDocumentPath25=
+OutputVariantName25=
+OutputDefault25=0
+PageOptions25=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType26=Text Print
+OutputName26=Text Print
+OutputDocumentPath26=
+OutputVariantName26=
+OutputDefault26=0
+PageOptions26=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType27=Text Print
+OutputName27=Text Print
+OutputDocumentPath27=
+OutputVariantName27=
+OutputDefault27=0
+PageOptions27=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType28=Text Print
+OutputName28=Text Print
+OutputDocumentPath28=
+OutputVariantName28=
+OutputDefault28=0
+PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType29=Text Print
+OutputName29=Text Print
+OutputDocumentPath29=
+OutputVariantName29=
+OutputDefault29=0
+PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+
+[OutputGroup8]
+Name=Validation Outputs
+Description=
+TargetPrinter=HP Deskjet 4620 series (Network)
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Component states check
+OutputName1=Vault's components states check
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+OutputType2=Configuration compliance
+OutputName2=Environment configuration compliance check
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+OutputType3=Design Rules Check
+OutputName3=Design Rules Check
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType4=Differences Report
+OutputName4=Differences Report
+OutputDocumentPath4=
+OutputVariantName4=
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=Electrical Rules Check
+OutputName5=Electrical Rules Check
+OutputDocumentPath5=
+OutputVariantName5=
+OutputDefault5=0
+PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType6=Footprint Comparison Report
+OutputName6=Footprint Comparison Report
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+
+[OutputGroup9]
+Name=Export Outputs
+Description=
+TargetPrinter=HP Deskjet 4620 series (Network)
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=AutoCAD dwg/dxf PCB
+OutputName1=AutoCAD dwg/dxf File PCB
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+OutputType2=AutoCAD dwg/dxf Schematic
+OutputName2=AutoCAD dwg/dxf File Schematic
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+OutputType3=ExportIDF
+OutputName3=Export IDF
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+OutputType4=ExportPARASOLID
+OutputName4=Export PARASOLID
+OutputDocumentPath4=
+OutputVariantName4=[No Variations]
+OutputDefault4=0
+OutputType5=ExportSTEP
+OutputName5=Export STEP
+OutputDocumentPath5=
+OutputVariantName5=[No Variations]
+OutputDefault5=0
+OutputType6=ExportVRML
+OutputName6=Export VRML
+OutputDocumentPath6=
+OutputVariantName6=[No Variations]
+OutputDefault6=0
+OutputType7=Save As/Export PCB
+OutputName7=Save As/Export PCB
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+OutputType8=Save As/Export Schematic
+OutputName8=Save As/Export Schematic
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+OutputType9=Specctra Design PCB
+OutputName9=Specctra Design PCB
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+
+[OutputGroup10]
+Name=PostProcess Outputs
+Description=
+TargetPrinter=HP Deskjet 4620 series (Network)
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Copy Files
+OutputName1=Copy Files
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+
+[Modification Levels]
+Type1=1
+Type2=1
+Type3=1
+Type4=1
+Type5=1
+Type6=1
+Type7=1
+Type8=1
+Type9=1
+Type10=1
+Type11=1
+Type12=1
+Type13=1
+Type14=1
+Type15=1
+Type16=1
+Type17=1
+Type18=1
+Type19=1
+Type20=1
+Type21=1
+Type22=1
+Type23=1
+Type24=1
+Type25=1
+Type26=1
+Type27=1
+Type28=1
+Type29=1
+Type30=1
+Type31=1
+Type32=1
+Type33=1
+Type34=1
+Type35=1
+Type36=1
+Type37=1
+Type38=1
+Type39=1
+Type40=1
+Type41=1
+Type42=1
+Type43=1
+Type44=1
+Type45=1
+Type46=1
+Type47=1
+Type48=1
+Type49=1
+Type50=1
+Type51=1
+Type52=1
+Type53=1
+Type54=1
+Type55=1
+Type56=1
+Type57=1
+Type58=1
+Type59=1
+Type60=1
+Type61=1
+Type62=1
+Type63=1
+Type64=1
+Type65=1
+Type66=1
+Type67=1
+Type68=1
+Type69=1
+Type70=1
+Type71=1
+Type72=1
+Type73=1
+Type74=1
+Type75=1
+Type76=1
+Type77=1
+Type78=1
+Type79=1
+Type80=1
+Type81=1
+Type82=1
+Type83=1
+Type84=1
+Type85=1
+Type86=1
+Type87=1
+Type88=1
+Type89=1
+Type90=1
+
+[Difference Levels]
+Type1=1
+Type2=1
+Type3=1
+Type4=1
+Type5=1
+Type6=1
+Type7=1
+Type8=1
+Type9=1
+Type10=1
+Type11=1
+Type12=1
+Type13=1
+Type14=1
+Type15=1
+Type16=1
+Type17=1
+Type18=1
+Type19=1
+Type20=1
+Type21=1
+Type22=1
+Type23=1
+Type24=1
+Type25=1
+Type26=1
+Type27=1
+Type28=1
+Type29=1
+Type30=1
+Type31=1
+Type32=1
+Type33=1
+Type34=1
+Type35=1
+Type36=1
+Type37=1
+Type38=1
+Type39=1
+Type40=1
+Type41=1
+Type42=1
+Type43=1
+Type44=1
+Type45=1
+Type46=1
+Type47=1
+Type48=1
+Type49=1
+
+[Electrical Rules Check]
+Type1=1
+Type2=1
+Type3=2
+Type4=1
+Type5=2
+Type6=2
+Type7=1
+Type8=1
+Type9=1
+Type10=1
+Type11=2
+Type12=2
+Type13=2
+Type14=1
+Type15=1
+Type16=1
+Type17=1
+Type18=1
+Type19=1
+Type20=1
+Type21=1
+Type22=1
+Type23=1
+Type24=1
+Type25=2
+Type26=2
+Type27=2
+Type28=1
+Type29=1
+Type30=1
+Type31=1
+Type32=2
+Type33=2
+Type34=2
+Type35=1
+Type36=2
+Type37=1
+Type38=2
+Type39=2
+Type40=2
+Type41=0
+Type42=2
+Type43=1
+Type44=1
+Type45=2
+Type46=1
+Type47=2
+Type48=2
+Type49=1
+Type50=2
+Type51=1
+Type52=1
+Type53=1
+Type54=1
+Type55=1
+Type56=2
+Type57=1
+Type58=1
+Type59=2
+Type60=1
+Type61=2
+Type62=2
+Type63=1
+Type64=0
+Type65=2
+Type66=3
+Type67=2
+Type68=2
+Type69=2
+Type70=2
+Type71=2
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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===================================================================
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/izolirana_perfuzija_udov/Hardware/Libraries/Magistrska/History/mag_schematic_lib.~(63).SchLib.Zip
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===================================================================
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/izolirana_perfuzija_udov/Hardware/Libraries/Magistrska/History/mag_schematic_lib.~(64).SchLib.Zip
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===================================================================
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/izolirana_perfuzija_udov/Hardware/Libraries/Magistrska/History/mag_schematic_lib.~(65).SchLib.Zip
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===================================================================
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+OutputVariantName4=
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=PCBDrawing
+OutputName5=Draftsman
+OutputDocumentPath5=
+OutputVariantName5=[No Variations]
+OutputDefault5=0
+PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType6=PCBLIB Print
+OutputName6=PCBLIB Prints
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType7=PDF3D
+OutputName7=PDF3D
+OutputDocumentPath7=
+OutputVariantName7=[No Variations]
+OutputDefault7=0
+PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType8=Report Print
+OutputName8=Report Prints
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType9=Schematic Print
+OutputName9=Schematic Prints
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType10=SimView Print
+OutputName10=SimView Prints
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType11=Wave Print
+OutputName11=Wave Prints
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType12=WaveSim Print
+OutputName12=WaveSim Prints
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+
+[OutputGroup4]
+Name=Assembly Outputs
+Description=
+TargetPrinter=HP Deskjet 4620 series (Network)
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Assembly
+OutputName1=Assembly Drawings
+OutputDocumentPath1=
+OutputVariantName1=[No Variations]
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=Pick Place
+OutputName2=Generates pick and place files
+OutputDocumentPath2=
+OutputVariantName2=[No Variations]
+OutputDefault2=0
+OutputType3=Test Points For Assembly
+OutputName3=Test Point Report
+OutputDocumentPath3=
+OutputVariantName3=[No Variations]
+OutputDefault3=0
+
+[OutputGroup5]
+Name=Fabrication Outputs
+Description=
+TargetPrinter=HP Deskjet 4620 series (Network)
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Board Stack Report
+OutputName1=Report Board Stack
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=CompositeDrill
+OutputName2=Composite Drill Drawing
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType3=Drill
+OutputName3=Drill Drawing/Guides
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType4=Final
+OutputName4=Final Artwork Prints
+OutputDocumentPath4=
+OutputVariantName4=[No Variations]
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=Gerber
+OutputName5=Gerber Files
+OutputDocumentPath5=
+OutputVariantName5=[No Variations]
+OutputDefault5=0
+OutputType6=Gerber X2
+OutputName6=Gerber X2 Files
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+OutputType7=IPC2581
+OutputName7=IPC-2581 Files
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+OutputType8=Mask
+OutputName8=Solder/Paste Mask Prints
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType9=NC Drill
+OutputName9=NC Drill Files
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+OutputType10=ODB
+OutputName10=ODB++ Files
+OutputDocumentPath10=
+OutputVariantName10=[No Variations]
+OutputDefault10=0
+OutputType11=Plane
+OutputName11=Power-Plane Prints
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType12=Test Points
+OutputName12=Test Point Report
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+
+[OutputGroup6]
+Name=Report Outputs
+Description=
+TargetPrinter=HP Deskjet 4620 series (Network)
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=BOM_PartType
+OutputName1=Bill of Materials
+OutputDocumentPath1=
+OutputVariantName1=[No Variations]
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=ComponentCrossReference
+OutputName2=Component Cross Reference Report
+OutputDocumentPath2=
+OutputVariantName2=[No Variations]
+OutputDefault2=0
+OutputType3=ReportHierarchy
+OutputName3=Report Project Hierarchy
+OutputDocumentPath3=
+OutputVariantName3=[No Variations]
+OutputDefault3=0
+OutputType4=Script
+OutputName4=Script Output
+OutputDocumentPath4=
+OutputVariantName4=[No Variations]
+OutputDefault4=0
+OutputType5=SimpleBOM
+OutputName5=Simple BOM
+OutputDocumentPath5=
+OutputVariantName5=[No Variations]
+OutputDefault5=0
+OutputType6=SinglePinNetReporter
+OutputName6=Report Single Pin Nets
+OutputDocumentPath6=
+OutputVariantName6=[No Variations]
+OutputDefault6=0
+
+[OutputGroup7]
+Name=Other Outputs
+Description=
+TargetPrinter=HP Deskjet 4620 series (Network)
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Text Print
+OutputName1=Text Print
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=Text Print
+OutputName2=Text Print
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType3=Text Print
+OutputName3=Text Print
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType4=Text Print
+OutputName4=Text Print
+OutputDocumentPath4=
+OutputVariantName4=
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=Text Print
+OutputName5=Text Print
+OutputDocumentPath5=
+OutputVariantName5=
+OutputDefault5=0
+PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType6=Text Print
+OutputName6=Text Print
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType7=Text Print
+OutputName7=Text Print
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType8=Text Print
+OutputName8=Text Print
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType9=Text Print
+OutputName9=Text Print
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType10=Text Print
+OutputName10=Text Print
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType11=Text Print
+OutputName11=Text Print
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType12=Text Print
+OutputName12=Text Print
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType13=Text Print
+OutputName13=Text Print
+OutputDocumentPath13=
+OutputVariantName13=
+OutputDefault13=0
+PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType14=Text Print
+OutputName14=Text Print
+OutputDocumentPath14=
+OutputVariantName14=
+OutputDefault14=0
+PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType15=Text Print
+OutputName15=Text Print
+OutputDocumentPath15=
+OutputVariantName15=
+OutputDefault15=0
+PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType16=Text Print
+OutputName16=Text Print
+OutputDocumentPath16=
+OutputVariantName16=
+OutputDefault16=0
+PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType17=Text Print
+OutputName17=Text Print
+OutputDocumentPath17=
+OutputVariantName17=
+OutputDefault17=0
+PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType18=Text Print
+OutputName18=Text Print
+OutputDocumentPath18=
+OutputVariantName18=
+OutputDefault18=0
+PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType19=Text Print
+OutputName19=Text Print
+OutputDocumentPath19=
+OutputVariantName19=
+OutputDefault19=0
+PageOptions19=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType20=Text Print
+OutputName20=Text Print
+OutputDocumentPath20=
+OutputVariantName20=
+OutputDefault20=0
+PageOptions20=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType21=Text Print
+OutputName21=Text Print
+OutputDocumentPath21=
+OutputVariantName21=
+OutputDefault21=0
+PageOptions21=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType22=Text Print
+OutputName22=Text Print
+OutputDocumentPath22=
+OutputVariantName22=
+OutputDefault22=0
+PageOptions22=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType23=Text Print
+OutputName23=Text Print
+OutputDocumentPath23=
+OutputVariantName23=
+OutputDefault23=0
+PageOptions23=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType24=Text Print
+OutputName24=Text Print
+OutputDocumentPath24=
+OutputVariantName24=
+OutputDefault24=0
+PageOptions24=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType25=Text Print
+OutputName25=Text Print
+OutputDocumentPath25=
+OutputVariantName25=
+OutputDefault25=0
+PageOptions25=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType26=Text Print
+OutputName26=Text Print
+OutputDocumentPath26=
+OutputVariantName26=
+OutputDefault26=0
+PageOptions26=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType27=Text Print
+OutputName27=Text Print
+OutputDocumentPath27=
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+
+[Electrical Rules Check]
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Index: izolirana_perfuzija_udov/Hardware/Libraries/OpAmps.IntLib
===================================================================
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Index: izolirana_perfuzija_udov/Hardware/Libraries/PIC.IntLib
===================================================================
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===================================================================
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Index: izolirana_perfuzija_udov/Hardware/Libraries/RFID_master.IntLib
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===================================================================
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===================================================================
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Index: izolirana_perfuzija_udov/Hardware/Libraries/SemiCond/SemiCond.PCBLIB
===================================================================
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/izolirana_perfuzija_udov/Hardware/Libraries/SemiCond/SemiCond.PCBLIB
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Index: izolirana_perfuzija_udov/Hardware/Libraries/SemiCond/SemiCond.SchLib
===================================================================
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/izolirana_perfuzija_udov/Hardware/Libraries/SemiCond/SemiCond.SchLib
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===================================================================
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===================================================================
--- izolirana_perfuzija_udov/Hardware/Libraries/SemiCond.doc (nonexistent)
+++ izolirana_perfuzija_udov/Hardware/Libraries/SemiCond.doc (revision 336)
@@ -0,0 +1,37279 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<title>
+Integrated Library (Components) Report
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+<body bgcolor="#FFFFFF">
+<font face="Arial" size="2">
+<h1>
+Integrated Library (Components) Report
+</h1>
+<table border="0" cellspacing="0" cellpadding="4" width="100%">
+<tr>
+<td valign="top" width="30%">
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+Library File Date/Time
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+1. junij 2011 11:27:12
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+<b>
+Library File Size
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+715776
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+1N4001, 1N4148, 20BQ030, 2SJ613, 78XX_SOIC8, B250C800D, BC109, BC546, BC547, BC556, BC557, BC817, BRIDGE, BS107, BSP250, BSP603S2L, BSS138, BSS84P, BSS92, BZT52B5V1, BZX85C10, BZX85C11, BZX85C12, BZX85C13, BZX85C15, BZX85C16, BZX85C18, BZX85C20, BZX85C22, BZX85C24, BZX85C2V7, BZX85C3V0, BZX85C3V3, BZX85C3V6, BZX85C3V9, BZX85C4V3, BZX85C4V7, BZX85C5V1, BZX85C5V6, BZX85C6V2, BZX85C6V8, BZX85C7V5, BZX85C8V2, BZX85C9V1, D400, IRF512, IRF9620, IRL3715, IRL5602S, IRLMS4502, IRLZ44, MBRM130LT1G, PMEG2005EJ, SFP9620
+</font>
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+<hr>
+<table border="0" cellspacing="0" cellpadding="4" width="100%">
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+<tr>
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+1N4001
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+</h2>
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+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
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+1N4001
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+<font face="Arial" size="2">
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+2
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+</td>
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+Footprint
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+<font face="Arial" size="2">
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+</font>
+</td>
+</tr>
+<tr>
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+<font face="Arial" size="2">
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+</td>
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+HEX-FET Vdss=20V, Id=50A, Rdson=0.011R
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+</font>
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+D2-PAK, 3-Pads, Body 10,2x10,5mm (max), IPC Medium Density
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+Library Reference
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+0 Degrees
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+POWERMITE
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+<font face="Arial" size="2">
+No Symbol
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+No Symbol
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+No Symbol
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top">
+<font face="Arial" size="2">
+D
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+D
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+0mil
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+100mil
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+90 Degrees
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+Black
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+Passive
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+True
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+False
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+True
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+1
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+100mil
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+No Symbol
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+No Symbol
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+No Symbol
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+No Symbol
+</font>
+</td>
+</tr>
+</table>
+<h5>
+Models
+</h5>
+<table border="0" cellspacing="0" cellpadding="4" width="100%">
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<img src="Pro2471.wmf" width="238" height="256">
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+<table border="0" cellspacing="0" cellpadding="2" width="100%">
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Model Name
+</b>
+</font>
+</td>
+<td valign="top">
+<h3>
+<font face="Arial" size="2">
+TO-220AB horizontal
+</font>
+</h3>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Model Type
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+Footprint
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Description
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+&nbsp;
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Height
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+787.402mil
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Dimension
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+410mil x 794.433mil
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Number of Pads
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+4
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Number of Primitives
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+12
+</font>
+</td>
+</tr>
+</table>
+</font>
+</td>
+</tr>
+</table>
+&nbsp;
+<p>
+<table border="0" cellspacing="0" cellpadding="4" width="100%">
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<img src="Pro251E.wmf" width="256" height="179">
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+<table border="0" cellspacing="0" cellpadding="2" width="100%">
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Model Name
+</b>
+</font>
+</td>
+<td valign="top">
+<h3>
+<font face="Arial" size="2">
+TO-220AB vertical
+</font>
+</h3>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Model Type
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+Footprint
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Description
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+&nbsp;
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Height
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+787.402mil
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Dimension
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+448.731mil x 194mil
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Number of Pads
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+3
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Number of Primitives
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+12
+</font>
+</td>
+</tr>
+</table>
+</font>
+</td>
+</tr>
+</table>
+&nbsp;
+<p>
+<table border="0" cellspacing="0" cellpadding="4" width="100%">
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<img src="Pro25BB.wmf" width="256" height="252">
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+<table border="0" cellspacing="0" cellpadding="2" width="100%">
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Model Name
+</b>
+</font>
+</td>
+<td valign="top">
+<h3>
+<font face="Arial" size="2">
+TO-220AB vertical + HS
+</font>
+</h3>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Model Type
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+Footprint
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Description
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+&nbsp;
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Height
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+787.402mil
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Dimension
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+1208.161mil x 1190.191mil
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Number of Pads
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+3
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Number of Primitives
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+15
+</font>
+</td>
+</tr>
+</table>
+</font>
+</td>
+</tr>
+</table>
+&nbsp;
+<p>
+<table border="0" cellspacing="0" cellpadding="4" width="100%">
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<img src="Pro2668.wmf" width="256" height="179">
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+<table border="0" cellspacing="0" cellpadding="2" width="100%">
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Model Name
+</b>
+</font>
+</td>
+<td valign="top">
+<h3>
+<font face="Arial" size="2">
+TO-220AB vertical + HS2
+</font>
+</h3>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Model Type
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+Footprint
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Description
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+&nbsp;
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Height
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+787.402mil
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Dimension
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+679mil x 411.996mil
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Number of Pads
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+3
+</font>
+</td>
+</tr>
+<tr>
+<td valign="top" width="30%">
+<font face="Arial" size="2">
+<b>
+Number of Primitives
+</b>
+</font>
+</td>
+<td valign="top">
+<font face="Arial" size="2">
+16
+</font>
+</td>
+</tr>
+</table>
+</font>
+</td>
+</tr>
+</table>
+&nbsp;
+<p>
+</font>
+</body>
+</html>
Index: izolirana_perfuzija_udov/Hardware/Libraries/Telit.IntLib
===================================================================
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/izolirana_perfuzija_udov/Hardware/Libraries/Telit.IntLib
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Index: izolirana_perfuzija_udov/Hardware/Libraries/mag_pcb_lib.PcbLib
===================================================================
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/izolirana_perfuzija_udov/Hardware/Libraries/mag_pcb_lib.PcbLib
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Index: izolirana_perfuzija_udov/Hardware/PCB_fotopmn.PcbDoc
===================================================================
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/izolirana_perfuzija_udov/Hardware/PCB_fotopmn.PcbDoc
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Index: izolirana_perfuzija_udov/Hardware/PCB_nap.PcbDoc
===================================================================
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/izolirana_perfuzija_udov/Hardware/PCB_nap.PcbDoc
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+application/octet-stream
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Index: izolirana_perfuzija_udov/Hardware/PCB_sig.PcbDoc
===================================================================
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/izolirana_perfuzija_udov/Hardware/PCB_sig.PcbDoc
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Index: izolirana_perfuzija_udov/Hardware/fotopomnozevalka.SchDoc
===================================================================
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/izolirana_perfuzija_udov/Hardware/fotopomnozevalka.SchDoc
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Index: izolirana_perfuzija_udov/Hardware/high_voltage_circuit.SchDoc
===================================================================
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/izolirana_perfuzija_udov/Hardware/high_voltage_circuit.SchDoc
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Index: izolirana_perfuzija_udov/Hardware/napajanje.SchDoc
===================================================================
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/izolirana_perfuzija_udov/Hardware/napajanje.SchDoc
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Index: izolirana_perfuzija_udov/Hardware/obdelava_signala.SchDoc
===================================================================
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/izolirana_perfuzija_udov/Hardware/obdelava_signala.SchDoc
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Index: izolirana_perfuzija_udov/Red Pitaya/C/data_handling.c
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/C/data_handling.c (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/C/data_handling.c (revision 336)
@@ -0,0 +1,222 @@
+/*
+ * data_handling.c
+ *
+ * Created on: 18. dec. 2018
+ * Author: Domen
+ */
+
+#include <stdint.h>
+#include "data_handling.h"
+#include <sys/mman.h>
+
+
+/*----------------------------------STATIC FUNCTIONS PROTOTYPES---------------------------------*/
+
+uint32_t read__value(uint32_t *addr);
+void write_value (uint32_t *addr, uint32_t value);
+
+
+
+
+
+
+
+
+
+
+
+/* -----------------------------------------STATIC (PRIVATE) FUNCTIONS----------------------------------*/
+
+
+uint32_t read_value(uint32_t *addr) //mogoce dodaj *
+{
+
+
+ uint32_t result = 0;
+
+ result = *(addr);
+
+ return result;
+}
+
+
+
+void write_value(uint32_t *addr, uint32_t value)
+{
+ *addr = value;
+}
+
+
+
+
+
+
+
+/*-----------------------------------------PUBLIC FUNCTIONS----------------------------------*/
+
+uint32_t *HW_init(void)
+{
+
+ void *map_base = (void *)(-1); //naslov, kjer se mi zacne mapiran spomin
+ static void *virt_addr;
+ int fd = -1; //file descriptor
+
+
+
+ //odpiram svoj file
+ if ( (fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1 )
+ {
+ perror("ERROR: open."); //sporoci napako, ce ni OK odprl
+ }
+
+
+ //mapiram memmory v zgoraj odprtem file-u in preverjam, ce se je OK odprl
+ map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, HW_address & ~MAP_MASK); //zakaj ni tukaj za offset kar samo HW_address
+
+ if(map_base == (void *) -1)
+ {
+ perror("ERROR: mmap ni pravilno lociral spomina");
+ }
+
+ printf("MAP_BASE: %p\n",map_base);
+ virt_addr = map_base + (HW_address & MAP_MASK); //ne vem, ce to potrebno, ker bi moral ze v map_base imeti pravi naslov
+ virt_addr = (uint32_t *)virt_addr; //castam na uint32_t, da ga read_value lahko sprejme
+
+
+ /* map base bi mi ze moral vrniti moj pravi HW_naslov, se pravi 0x40500000, ker
+ * v funkciji mmap dodam offset, kje naj locira pomnilnik: zaène na NULL v /dev/mem, offset pa je HW_address & ~MAP_MASK
+ * kar je enako 0x40500000, maska poskrbi samo za to, da je spodnjih 12 bitov na 0, ker so memory blocks poravnani na
+ * zaèetek strani (glej tole: https://www.youtube.com/watch?v=XV5sRaSVtXQ at 5.20)
+ *
+ *
+ */
+
+
+
+ return virt_addr;
+}
+
+
+
+
+
+uint8_t HW_comm ( HW_system *strct, uint32_t *reg_addr)
+{
+ uint32_t HW_write = 0;
+ uint32_t HW_read = 0;
+
+
+ if ( (strct -> HW_config_flag) == 1 )
+ {
+ //pisanje ukazov v register
+ HW_write = ( (strct -> start) |
+ ((strct -> reset) << 1) |
+ ((strct -> threshold) << 8) |
+ ((strct -> acq_window) << 19) |
+ ((strct -> sw_trigger) << 27)
+ );
+ //*reg_addr = HW_write;
+ write_value(reg_addr, HW_write);
+ //printf("VPIS v HW:0x%08x\n",HW_write);
+ return 1; //sistem nastavljen
+ }
+
+ //branje histograma iz registra in shranjevanje podatkov v strukturo
+ else if ( (strct -> send_data_flag) == 1)
+ {
+ HW_read = read_value(reg_addr);
+
+ (strct -> UC_rd_en_current) = (HW_read & UC_rd_en_current_mask) >> 1;
+ (strct -> UC_rd_en_final) = (HW_read & UC_rd_en_final_mask);
+ (strct -> hist_data) = (HW_read & HIST_MASK) >> 8 ;
+
+
+ //printf("PREBRANI PODATKI:0x%08x\n",HW_read);
+ //printf("UC_rd_en_current: 0x%08x\n ",strct ->UC_rd_en_current);
+
+
+
+ return 2; //podatki pripravljeni za posiljanje v PC
+ }
+
+ else
+ return 0;
+
+}
+
+
+
+
+
+
+ /*
+
+ //------------TRENUTNI HISTOGRAM-----------
+ for (int idx=0; idx<BIN_NUM; idx++)
+ {
+
+ HW_read = read_value(reg_addr);
+
+ (strct -> UC_rd_en_current) = HW_read & UC_rd_en_current_mask;
+ (strct -> UC_rd_en_final) = HW_read & UC_rd_en_final_mask;
+
+
+ if ( (HW_read & UC_rd_en_final_mask) == UC_rd_en_final_mask ) //prisel je koncni histogram, ne vpisuj vec v trenutnega
+ {
+ break;
+ }
+ else
+ {
+ //(strct -> hist_idx) = idx;
+ (strct -> hist_data+idx) = HW_read & HIST_MASK;
+ }
+
+
+ if(idx == BIN_NUM -1)
+ {
+ return 1;
+ }
+ }
+
+
+ //------------------KONCNI HISTOGRAM----------------
+ if ( (strct -> UC_rd_en_final) == 1 && (strct -> UC_rd_en_current) == 0 )
+ {
+ (strct -> hist_data + 0) = HW_read & HIST_MASK; //vpis prvega podatka koncnega histograma
+
+ for (int idx=1; idx<BIN_NUM; idx++)
+ {
+ HW_read = read_value(reg_addr);
+
+ (strct -> UC_rd_en_current) = HW_read & UC_rd_en_current_mask;
+ (strct -> UC_rd_en_final) = HW_read & UC_rd_en_final_mask;
+ //(strct -> hist_idx) = idx;
+ (strct -> hist_data+idx) = HW_read & HIST_MASK;
+ }
+
+
+ if(idx == BIN_NUM -1)
+ {
+ return 1;
+ }
+
+ }
+ */
+
+
+// }
+
+//}
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: izolirana_perfuzija_udov/Red Pitaya/C/data_handling.h
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/C/data_handling.h (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/C/data_handling.h (revision 336)
@@ -0,0 +1,78 @@
+/*
+ * data_handling.h
+ *
+ * Created on: 18. dec. 2018
+ * Author: Domen
+ */
+
+#ifndef SRC_DATA_HANDLING_H_
+#define SRC_DATA_HANDLING_H_
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <fcntl.h>
+#include <math.h>
+//#include <sys/mman.h>
+
+
+
+
+
+
+#define HW_address 0x40500000
+#define MAP_SIZE 4096UL //size of a /dev/mem file, potrebujem, ko pri funkciji mmap
+#define MAP_MASK (MAP_SIZE - 1)
+
+
+#define BIN_NUM 1024
+#define UC_rd_en_final_mask 0x00000001
+#define UC_rd_en_current_mask 0x00000002
+#define HIST_MASK 0xFFFFFF00
+
+
+
+
+
+
+typedef struct
+{
+ /* ****** PC --> procesor --> FPGA ****** */
+ uint32_t start; // zastavica za zagon sistema
+ uint32_t reset; // zastavica za ponastavitev sistema
+ uint32_t HW_config_flag; // zahteva za nastavitev parametrov FPGA vezja
+ uint32_t send_data_flag; // zahteva za posiljanje podatkov v PC
+ uint32_t disconnect_flag; // zahteva za prekinitev povezave procesor - PC
+ uint32_t threshold; // pragovna vrednost za komponento ADC_unit
+ uint32_t acq_window; //casovno okno zajemanja za komponento ADC_unit
+ uint32_t sw_trigger; // pragovna vrednost za prozenje integratorja
+
+ /* ****** FPGA --> procesor --> PC ****** */
+ uint32_t hist_data; // stolpec histograma
+ uint32_t UC_rd_en_current; // sprotni histogram
+ uint32_t UC_rd_en_final; // koncni histogram
+
+} HW_system;
+
+
+
+//PUBLIC FUNCTION PROTOTYPES
+uint32_t *HW_init(void);
+uint8_t HW_comm( HW_system *strct, uint32_t *reg_addr);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#endif /* SRC_DATA_HANDLING_H_ */
Index: izolirana_perfuzija_udov/Red Pitaya/C/main.c
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/C/main.c (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/C/main.c (revision 336)
@@ -0,0 +1,61 @@
+/*
+ * main.c
+ *
+ * Created on: 18. dec. 2018
+ * Author: Domen
+ */
+
+/* MAIN PROGRAM */
+
+#include "data_handling.h"
+#include "server.h"
+
+
+
+HW_system system_data = {0,0,0,0,0,0,0,0,0,0};
+volatile const HW_system system_data_init = {0,0,0,0,0,0,0,0,0,0};
+
+
+int main(void)
+{
+
+ int server_info[2]; //sock_server in sock_client: PC_client; //ID PC clienta
+ uint32_t *virt_addr_ptr; // virtualni naslov, kjer so podatki v HW
+ static uint8_t data_status; // flag, ki pove, da se je vpis HW podatkov v strukturo ze vsaj 1x izvedel
+
+
+ while(1)
+ {
+ server_info[0] = 0; // sock_server
+ server_info[1] = 0; //sock_client
+
+ //PC_client = 0;
+ data_status = 0;
+
+ //SERVER AND HARDWARE INIT
+ Server_init(server_info);
+ virt_addr_ptr = HW_init();
+
+
+ // DATA HANDLING
+ while(1)
+ {
+ Server_comm(server_info, &system_data, data_status);
+ data_status = HW_comm(&system_data, virt_addr_ptr);
+
+ if (system_data.disconnect_flag == 1)
+ {
+ //system_data.disconnect_flag = 0; //ponastavi flag
+ system_data = system_data_init;
+ printf("Server disconnected\n!");
+ break;
+ }
+ //sleep(1);
+ }
+
+ }
+
+}
+
+
+
Index: izolirana_perfuzija_udov/Red Pitaya/C/server.c
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/C/server.c (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/C/server.c (revision 336)
@@ -0,0 +1,157 @@
+/*
+ * server.c
+ *
+ * Created on: 18. dec. 2018
+ * Author: Domen
+ */
+
+#include "server.h"
+//#include "data_handling.h" je ze definiran v server.h
+
+
+
+
+
+
+
+
+/*-------------------------------PUBLIC FUNCTIONS----------------------------------*/
+
+int Server_init(int *server_info)
+{
+
+ int sock_server;
+ int sock_client;
+ int enable = 1;
+ struct sockaddr_in addr;
+
+
+
+
+
+ if ( (sock_server = socket(AF_INET, SOCK_STREAM, 0)) < 0) //create an endpoint for communication
+ {
+ perror ("ERROR:socket");
+ return EXIT_FAILURE;
+ }
+
+
+ setsockopt(sock_server, SOL_SOCKET, SO_REUSEADDR, (void *)&enable, sizeof(enable)); //set the socket options
+
+ //setup listening address (setup server address v flowchartu)
+ memset(&addr, 0, sizeof(addr)); //copy 0 to the first sizeof(addr) characters of the string, pointet by the &addr
+ addr.sin_family = AF_INET;
+ addr.sin_addr.s_addr = htonl(INADDR_ANY); //poslusaj na vseh IP naslovih //htonl converts the unsinged int hostlong from host byte order to netword byte order
+ addr.sin_port = htons(1001); //Red pitaya port = 1001; //htons je isto kot htonl, samo da za short integerje
+
+
+ if (bind(sock_server, (struct sockaddr *)&addr, sizeof(addr)) < 0) //bind poveze ustvarjen socket (sock_server) z naslovom (stvar pod komentarjem setup listening address)
+ {
+ perror("ERROR:bind");
+ return EXIT_FAILURE;
+ }
+
+ listen(sock_server,1024); //poskusa vzpostaviti povezavo, to naredi 1024x.
+ printf("Listening on port 1001 ... \n");
+
+
+
+ if( (sock_client = accept(sock_server, NULL, NULL)) < 0)
+ {
+ perror("ERROR: accept");
+ return EXIT_FAILURE;
+ }
+
+ else
+ {
+
+ server_info[0] = sock_server; //zlozim podatke o serverju v tabelo
+ server_info[1] = sock_client;
+ printf("Server_init funcija pride do konca. Vrne sock client:%d",sock_client);
+
+ return 0;
+
+
+ }
+
+
+}
+
+
+
+
+void Server_comm(int* server_info, HW_system *strct, int status)
+{
+ int bytes_rec;
+ uint32_t data_from_PC;
+ uint32_t data_for_PC;
+
+ int Server_ID = server_info[0];
+ int Client_ID = server_info[1];
+
+ int sent = 0; //za test
+ static int do_it_once = 0;
+
+
+ //PREJEMANJE PODATKOV OD PC-JA:
+ bytes_rec = recv(Client_ID, &data_from_PC, 4, MSG_DONTWAIT); // vpise prejete podatke v data_from_PC in vrne, kolk bajtov je prejel v bytes_rec
+
+ if (bytes_rec == 4) //vpis prejetih podatkov v strukturo
+ {
+
+ (strct -> start) = data_from_PC & START_MASK;
+ (strct -> reset) = (data_from_PC & RESET_MASK) >> 1;
+ (strct -> HW_config_flag) = (data_from_PC & HW_CONFIG_MASK) >> 2;
+ (strct -> send_data_flag) = (data_from_PC & SEND_DATA_MASK) >> 3;
+ (strct -> disconnect_flag) = (data_from_PC & DISCONNECT_MASK) >> 4;
+ (strct -> threshold) = (data_from_PC & THRESHOLD_MASK) >> 8;
+ (strct -> acq_window) = (data_from_PC & ACQ_WINDOW_MASK) >> 19;
+ (strct -> sw_trigger) = (data_from_PC & SW_TRIGGER_MASK) >> 27;
+
+ //za test
+ //printf("Podatki, prejeti od PC-ja: 0x%08x\n",data_from_PC);
+ }
+
+ else
+ {
+ //printf("Ni blo 4 bajtov, prislo je %d bajtov.\n", bytes_rec);
+ }
+
+
+ //------------------------------NOTIFICATIONS ZA TEST-------------------------------------------------
+ if((strct -> reset)==1) printf("Sistem RESET\n");
+
+ //-----------------------------------------------------------------------------------------------------
+
+ //POSILJANJE PODATKOV V PC:
+ if ( ((strct -> send_data_flag) == 1) && (status == 2) )
+ {
+ data_for_PC = ( (strct -> hist_data) << 8 ) | ( (strct -> UC_rd_en_current) << 1 ) | (strct -> UC_rd_en_final);
+ sent = send(Client_ID,&data_for_PC, 4, MSG_NOSIGNAL); //&data_for_PC
+ printf("Poslano %d bajtov.\n",sent);
+
+ //ko pride final histogram, ugasni prejemanje, da ga potem PC spet zazene in se ne prehiteva
+ if ( (strct -> UC_rd_en_final) == 1 && do_it_once == 0)
+ {
+ (strct -> send_data_flag) = 0;
+ //printf("Poslan prvi podatek koncnega histograma. Ugasam posiljanje!");
+ do_it_once = 1;
+ }
+
+ else if ((strct -> UC_rd_en_current == 1))
+ {
+ do_it_once = 0;
+ }
+ }
+
+ //TODO: zapiranje serverja in clienta
+ if ((strct -> disconnect_flag) == 1)
+ {
+ close(Client_ID);
+ close(Server_ID);
+ }
+
+
+}
+
+
Index: izolirana_perfuzija_udov/Red Pitaya/C/server.h
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/C/server.h (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/C/server.h (revision 336)
@@ -0,0 +1,48 @@
+/*
+ * server.h
+ *
+ * Created on: 18. dec. 2018
+ * Author: Domen
+ */
+
+#ifndef SRC_SERVER_H_
+#define SRC_SERVER_H_
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <math.h>
+//#include <sys/mman.h> // X
+#include <sys/socket.h> // za uporabo funkcij za TCP/IP povezavo
+#include <netinet/in.h> //neke type definira
+#include <arpa/inet.h> //definira type za net, funkcija htonl spada sem
+#include "data_handling.h"
+
+
+#define START_MASK 0x00000001
+#define RESET_MASK 0x00000002
+#define HW_CONFIG_MASK 0x00000004
+#define SEND_DATA_MASK 0x00000008
+#define DISCONNECT_MASK 0x00000010
+#define THRESHOLD_MASK 0x0007FF00
+#define ACQ_WINDOW_MASK 0x07F80000
+#define SW_TRIGGER_MASK 0xF8000000
+
+
+
+/*------------------PUBLIC FUNCTIONS PROTOTYPES--------------------------*/
+void Server_comm(int *server_info, HW_system *strct, int status);
+int Server_init(int* server_info);
+
+
+
+
+
+
+
+
+#endif /* SRC_SERVER_H_ */
Index: izolirana_perfuzija_udov/Red Pitaya/FPGA/ADC_unit_2.vhd
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/FPGA/ADC_unit_2.vhd (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/FPGA/ADC_unit_2.vhd (revision 336)
@@ -0,0 +1,466 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 24.10.2018 17:44:30
+-- Design Name:
+-- Module Name: ADC_unit - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ADC_unit is
+
+ generic ( adc_bit_num : natural := 14; --input data from ad converter is 14 bit
+ bit_num : natural := 10; -- number of bits for our data (scaled from 14 bit to 10 bit)
+ num_of_units: natural := 2; -- number of BRAM_buffer and PE_unit units
+ buffer_size: natural := 5; --size of each BRAM_buffer in bits
+ mode: string := "MODE_3"; -- modes of operation: MODE_1 = navaden algoritm, MODE_2 = odklop bufferja in 1 enota, MODE_3 = novo od 30.11.2018 naprej
+ byte: natural := 8
+
+ );
+
+ port ( clk_in: in std_logic;
+ START: in std_logic; -- start the system
+ data_in : in unsigned ( (adc_bit_num - 1) downto 0 ); --data from ADC
+ ADC_unit_feedback: in std_logic;
+ AD_wr_en: out unsigned ( (num_of_units - 1) downto 0 );-- goes to BRAM_buffer, to AD_wr_en signal
+ AD_addr: out unsigned ( (buffer_size - 1) downto 0 ); -- goes to BRAM_buffer, address signal
+ data_out: out unsigned ( (bit_num - 1) downto 0 ); -- goes to data_in of BRAM_buffer
+ --MODE_3--
+ threshold: in unsigned ( (11 - 1) downto 0 ); --11 bitno zato, ker imam najvec 2048 kanalov
+ capt_num_of_samples: in unsigned ( (byte - 1) downto 0 ); --time window
+ INT_res: out std_logic;
+
+ SW_trigger_value: in unsigned(4 downto 0);
+ PM_trigger_in: in unsigned ( (adc_bit_num - 1) downto 0)
+ );
+
+end ADC_unit;
+
+architecture Behavioral of ADC_unit is
+
+
+------FUNCTIONS-----------------
+ function data_map( input: unsigned ( (adc_bit_num - 2) downto 0) := (others => '0'); --transforms data drom one region to the other (for example from 0 - 1023 to 0-512)
+ current_low: integer := 0;
+ current_high: integer := 0;
+ next_low: integer := 0;
+ next_high: integer := 0 ) return unsigned is
+
+ --variable result: real := 0.0;
+ variable output : integer := 0;
+
+ begin
+ output := ((to_integer(input) - current_low) * (next_high - next_low)) / (current_high - current_low) + next_low;
+ --TODO: zaokrozevanje
+ return to_unsigned(output,bit_num);
+ end function;
+
+
+
+--------------CONSTANTS------------------- (used for input arguments of function data_map)
+ constant adc_low: integer := 0; --old area low
+ constant adc_high: integer :=8191; --2**(adc_bit_num -1) - 1; --1443;-- --old area high , blo je adc_bit_num sam to pol se neg. del adc-ja zravn, kar nocm TODO: 12.4.2019, kalibriraj na novo vrednost
+ constant mapped_low: integer := 0; --new area low
+ constant mapped_high: integer := 2**bit_num - 1; -- new area high
+
+
+
+--------SIGNALS--------------------------
+
+ signal data_in_reduced: unsigned ( (adc_bit_num - 2) downto 0) := (others => '0'); -- 13 bitov rabm, da sam pozitivne vrednosti berem, negativnih ne
+
+ signal data_out_sig: unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
+
+ signal AD_addr_sig: unsigned ( (buffer_size - 1) downto 0) := (others =>'0');
+
+ signal absolute_addr: integer := 0; -- ta šteje število podatkov in pol to pretvarja v naslov za bram bufferje (AD_addr_sig = absolute_addr % (2**buffer_size)
+
+ signal unit: integer := 0;
+ signal unit_next: integer := 1;
+ signal last_unit: std_logic;-- := '0';
+
+ signal delay_cycles : integer := 0;
+ signal delay_cycles_2 : integer := 0;
+ signal delay_flag : boolean := FALSE;
+
+
+ --MODE 3 SIGNALI-----------------------------------------
+ --signal threshold_dig: unsigned ( (11 - 1) downto 0 ) := (others => '0'); -- threshold pride notr kot analogna vrednost, potem jo pretvorim v digialno in to zapisem v ta signal: POPRAVEK: zaenkrat ne bo tako, bom kar digitalno vrednost poslal, pretvorba iz analogne sledi v C-programu
+ signal data_in_mapped: unsigned ( (bit_num - 1) downto 0) := (others => '0'); -- pretvorjen data_in_reduced iz 13 bitov na 10 bitov
+ signal data_in_mapped_prev: unsigned ( (bit_num - 1) downto 0) := (others => '0'); --gledam prejsnjo vrednost, da dolocicm trenutek prehoda pod treshold
+ signal send_data_flag: std_logic := '0';
+
+ signal counter: unsigned ( (byte - 1) downto 0) := (others => '0');
+
+ signal int_res_sig: std_logic := '1'; --integrator reset signal 1: RESET , 0: INTEGRIRAJ
+ signal int_reset_time_cycles: integer := 40;--25; --25 ciklov * 8ns = 200ns
+ type integrator_mode is (INTEGRATE, RESET); -- stanji integratorja
+ signal int_state: integrator_mode := INTEGRATE;
+
+ signal trigger_in_reduced: unsigned ( (adc_bit_num - 2) downto 0) := (others => '0');
+ signal trigger_in_inverted: unsigned ( (adc_bit_num - 1) downto 0) := (others => '0');
+
+begin
+
+--DEL KODE, KI VELJA ZA VSE MODE
+data_in_reduced <= data_in(12 downto 0) when data_in(13) = '0' else -- vzemi samo pozitivne vrednosti, negativne na 0
+ (others => '0') when data_in(13) = '1';
+
+--trigger_in_reduced <= PM_trigger_in(12 downto 0) when PM_trigger_in(13) = '1' else --za vsak slucaj, ce ne gre po dvojiskem komplementu
+ -- (others => '0');
+
+trigger_in_inverted <= (not(PM_trigger_in) + 1) when PM_trigger_in(13) = '1' else --dvojiski komplement, hocem pozitivno vrednost, je lazje primerjat
+ (others => '0');
+
+data_out <= data_out_sig;
+
+
+
+
+------------------------MODE_1 IN MODE_2 -------------------------------------------------------------------
+------------------------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------------------------
+
+
+
+MODE_1_MODE_2: if (mode = "MODE_1" or mode = "MODE_2") generate
+
+---COMBINATIONAL PART-------------------------------
+
+
+ AD_addr <= AD_addr_sig;
+
+
+ last_unit <= '1' when unit = num_of_units - 1 else
+ '0';
+
+
+---SEQUENTIAL PART------
+
+ Data_handling_1_2: process (clk_in)
+ variable end_flag: std_logic := '0';
+ variable first_flag: std_logic := '0';
+ variable delay_flag: boolean := FALSE;
+ begin
+
+ if (rising_edge(clk_in)) then
+
+ if (START = '1') then
+
+ if(num_of_units = 1) then
+
+ if(first_flag = '0') then --ko gres prvic skos
+ AD_wr_en(0) <= '1'; --prizgi PE_enoto
+
+ if(delay_cycles < 2) then --delay za 2 cikla
+ delay_cycles <= delay_cycles + 1;
+ end if;
+
+ if (delay_cycles = 2) then
+ -- naslovi in izhodni podatki
+ absolute_addr <= absolute_addr + 1;
+ AD_addr_sig <= to_unsigned( absolute_addr rem (2**buffer_size), buffer_size ); -- TODO: 30.11.2018 -- TEGA SPLOH NI TREBA, ker ne uporabljam tega signala v temu mode-u
+ data_out_sig <= data_map(data_in_reduced, adc_low, adc_high, mapped_low, mapped_high); -- isto kot komentar eno vrstico zgoraj
+ end if;
+
+ if (AD_addr_sig = 2**buffer_size - 2) then -- ce je -1 pol enga prevec nakonc vpise
+ AD_wr_en(0) <= '0';
+ delay_cycles <= 0;
+ first_flag := '1';
+ end if;
+
+ elsif(first_flag = '1') then --ideja: tale del das delay ene par ciklov, tolk da ADC_unit_feedback oz. UC_rd_en_sig ze na 1 skoc in pol gledas kdaj je naslednjic 0, to je pa glih takrt k rabs przgat spet
+
+ if (delay_cycles < 6) then --6 zato, ker tok cajta rab, da UC_wr_en skoc na '1'
+ delay_cycles <= delay_cycles + 1;
+ absolute_addr <= 0;
+ AD_addr_sig <= (others => '0');
+ end if;
+
+ if( delay_cycles = 6 and ADC_unit_feedback = '0' and AD_addr_sig < 2**buffer_size - 1 ) then --mislim, da addr in data out tukaj ne rabim prirejat, ker sem ga ze zgoraj
+ AD_wr_en(0) <= '1'; --ADC_unit_feedback je v tukaj UC_rd_en_sig, zarad muxa v hist_system_top
+ delay_cycles <= 6;
+
+ if(delay_cycles_2 < 2) then --delay za 2 cikla
+ delay_cycles_2 <= delay_cycles_2 + 1;
+ end if;
+
+ if (delay_cycles_2 = 2) then
+ absolute_addr <= absolute_addr + 1;
+ AD_addr_sig <= to_unsigned( absolute_addr rem (2**buffer_size), buffer_size ); -- isto kot v C-ju: absolute_addr % 2**buffer_size (ostanek pri deljenju)
+ data_out_sig <= data_map(data_in_reduced, adc_low, adc_high, mapped_low, mapped_high);
+ end if;
+ end if;
+
+ if (AD_addr_sig = 2** buffer_size - 2) then
+ AD_wr_en(0) <= '0';
+ delay_cycles <= 0;
+ delay_cycles_2 <= 0;
+ end if;
+
+ end if;
+
+
+
+ --ZA VEC ENOT-------------------------------------------
+ elsif (num_of_units /= 1 and ADC_unit_feedback = '0') then
+
+ -- naslovi in izhodni podatki
+ absolute_addr <= absolute_addr + 1;
+ AD_addr_sig <= to_unsigned( absolute_addr rem (2**buffer_size), buffer_size ); -- isto kot v C-ju: absolute_addr % 2**buffer_size (ostanek pri deljenju)
+ data_out_sig <= data_map(data_in_reduced, adc_low, adc_high, mapped_low, mapped_high);
+
+
+ --menjava enot
+ if (AD_addr_sig = 2**buffer_size - 1) then
+
+ if(unit < num_of_units - 2) then
+ unit <= unit_next;
+ unit_next <= unit_next + 1;
+
+ elsif (last_unit = '0') then --za zadnjo enoto
+ unit <= unit_next;
+ --unit_next <= unit_next;-- = kokr da nc ne napisem, pac ne povecam se enkrat
+ end if;
+
+ end if;
+
+
+
+ --priziganje in ugasanje enot
+ if (last_unit = '0') then --vse enote razen zadnje
+ if (AD_addr_sig < 2**buffer_size - 2 ) then
+
+ AD_wr_en(unit) <= '1';
+
+
+ elsif (AD_addr_sig = 2**buffer_size - 1) then
+ AD_wr_en(unit) <= '0';
+ AD_wr_en(unit_next) <= '1';
+
+ end if;
+
+ elsif (last_unit = '1') then --ugasni zadnjo en ob pravem casu, prizge se pa: - ko je last unit se 0, ce je vec enot
+ if (AD_addr_sig < 2**buffer_size -1 and end_flag = '0') then -- tukaj jo prizgem, ce je samo 1 enota
+ AD_wr_en(unit) <= '1';
+ else
+ AD_wr_en(unit) <= '0';
+ end_flag := '1'; --ko se AD_wr(unit) postavi na 0, se celotna elsif zanka potem se 1x izvede in AD_wr_en(unit) se
+ end if; -- spet postavi na '1', kar ni OK. V ta namen tukaj postavim flag, da zadnja enota res ostane na 0
+ end if; -- ko jo tukaj izklopim (pogoj, da bi se postavila na '1' v vrstici 162 ni izpolnjen)
+
+ elsif (num_of_units /= 1 and ADC_unit_feedback = '1') then --resetiraj za naslednje sprejemanje, ce je vec enot. ce tega ni, se vse samo 1x izvede
+ AD_wr_en <= (others => '0');
+ data_out_sig <= (others => '0');
+ AD_addr_sig <= (others => '0');
+ absolute_addr <= 0;
+ unit <= 0;
+ unit_next <= 1;
+ end_flag := '0';
+ end if;
+
+ else --reset everything when START = '0'--
+
+ AD_wr_en <= (others => '0');
+ data_out_sig <= (others => '0');
+ AD_addr_sig <= (others => '0');
+ absolute_addr <= 0;
+ unit <= 0;
+ unit_next <= 1;
+ delay_cycles <= 0;
+ delay_cycles_2 <= 0;
+ first_flag := '0';
+ end_flag := '0';
+ end if;
+
+
+
+ end if;
+
+ end process;
+
+end generate; --end of code for MODE_1 and MODE_2
+
+
+
+
+------------------------MODE_3 -------------------------------------------------------------------
+------------------------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------------------------
+MODE_3: if (mode = "MODE_3") generate
+
+----------COMBINATIONAL PART---------------------
+ INT_res <= int_res_sig; --SPREMENJENO 30.3.2019 -- not sm pobrisov, ker sm ga na zadnjem testiranju pomoje dodal, pa ga ni treba. 12-4.2019 -- vse dela ok
+
+----------SEQUENTIAL PART---------------------------
+
+ Data_handling_3: process (clk_in)
+
+ variable min_value: unsigned ( (bit_num - 1) downto 0) := (others => '0'); -- minimalna (zacetna) vrednost na intervalu integriranja
+ variable max_value: unsigned ( (bit_num - 1) downto 0) := (others => '0'); --maksimalna (koncna) vrednost na intervalu, ko integriramo
+ --variable counter: unsigned ( (byte - 1) downto 0) := (others => '0');
+ --variable go_measure: std_logic := '0';
+ variable do_it_once: std_logic := '0';
+ variable do_it_once_2: std_logic := '0';
+
+ begin
+
+ if ( rising_edge(clk_in) ) then
+
+ --TODO: pogoj ADC_unit_feedback, da enota ve, kdaj lahko posilja podatke -- 3.2.2019: tole pomoje mam
+
+ if (do_it_once = '0') then --tole samo zato, da ni na zacetku AD_wr_en(0) undefined
+ AD_wr_en(0) <= '0';
+ do_it_once := '1';
+ end if;
+
+
+ if ( START = '1' ) then
+
+ data_in_mapped <= data_map(data_in_reduced, adc_low, adc_high, mapped_low, mapped_high);
+
+ if (ADC_unit_feedback = '0' ) then
+
+ case int_state is
+
+ when INTEGRATE =>
+
+ int_res_sig <= '0'; --tole se uporabi samo prvic in samo prvic imam potem 1 clk zamude, ko pridem v INTEGRATE stanje, ker v ostalih primerih
+ -- sem ravno prisel iz RESET stanja, ki mi pa ze vklopi integriranje, prav zato, da ni 1 clk zamude pri zacetku integriranja
+ -- potem, ko pridem v INTEGRATE stanje
+
+ if( int_res_sig = '0') then --pogoj zato, da ga ze takoj ne poveca, ko pade int_res na 0 ,ampak z enim clockom zamude, ker je drugace cas integriranja za 1 clock napacen (prevelik)
+
+ if(do_it_once_2 = '0') then -- ta del pridobi vhodno vrednost na ADC na zacetku integriranja
+ min_value := data_in_mapped;
+ do_it_once_2 := '1';
+ end if;
+
+ counter <= counter + 1;
+
+
+-- if( counter < capt_num_of_samples - 1) then------------------------------------
+
+-- if(data_in_mapped >= threshold) then
+
+-- if(data_in_mapped > max_value) then
+-- --max_value := data_in_mapped; --SPREMENJENO 22.7.2019
+-- end if;
+
+-- end if;
+
+ if( counter = capt_num_of_samples - 1) then ---------------------------------
+
+
+ send_data_flag <= '1'; --poslji maksimalen podatek v PE enoto
+
+ --SPREMENJENO 22.7.2019
+ if (data_in_mapped >= threshold) then
+ data_out_sig <= data_in_mapped; --max_value; -- - min_value; --dodano
+ end if;
+
+
+ counter <= (others => '0');
+ --max_value := (others => '0');
+
+ int_res_sig <= '1'; --ustavi integriranje
+ int_state <= RESET; -- pojdi v reset stanje
+
+ end if; -----------------------------------------------------------------------
+
+ end if;
+
+
+ when RESET =>
+
+ do_it_once_2 := '0';
+ --------------VPIS PODATKA V PE_unit----------------
+ if (send_data_flag = '1' and data_out_sig >= threshold) then-- data_out_sig dodano, da ne vpisuje nicel , > threshold mogoce
+
+ send_data_flag <= '0'; -- KO SE data_out_sig POJAVI NA IZHODNEM VODILU, JE POTREBNO POCAKATI EN CLK,
+ AD_wr_en(0) <= '1'; --POTEM PA SELE VKLOPITI PISANJE (DA SE data_out PODATEK POJAVI NA old_value V PE_ENOTI)
+
+ else
+ AD_wr_en(0) <= '0';
+ send_data_flag <= '0'; --dodano
+ data_out_sig <= (others => '0'); --SPREMENJENO 22.7.2019 dodano
+ end if;
+
+ --------------ŠTETJE ÈASA PRAZNJENJA KONDENZATORJA------
+ if (delay_cycles < int_reset_time_cycles - 1) then
+ delay_cycles <= delay_cycles + 1; --koliko ciklov je preteklo od zaèetka resetiranja integratorja
+
+
+ elsif (delay_cycles = int_reset_time_cycles - 1) then
+ if(to_integer(trigger_in_inverted(12 downto 0)) >= (to_integer(SW_trigger_value) *5) ) then--if ( to_integer(trigger_in_reduced) >= (to_integer(SW_trigger_value) * 5)) then
+ int_res_sig <= '0'; --ze tukaj vklopi integriranje, da ni zamude po prihodu v INTEGRATE stanje
+ int_state <= INTEGRATE;
+ delay_cycles <= 0;
+ end if;
+ end if;
+
+ end case;
+
+
+ else -- ce je ADC_unit_feedback '1'
+ data_out_sig <= (others => '0');
+ AD_wr_en(0) <= '0';
+ max_value := (others => '0');
+ counter <= (others => '0');
+ send_data_flag <= '0';
+ int_res_sig <= '1'; -- izklopi integrator
+ delay_cycles <= 0;
+ do_it_once_2 := '0';
+
+ end if; --ADC_unit_feedback pogoj
+
+
+ else
+ do_it_once := '0';
+ do_it_once_2 := '0';
+ data_out_sig <= (others => '0');
+ AD_wr_en(0) <= '0';
+ max_value := (others => '0');
+ counter <= (others => '0');
+ send_data_flag <= '0';
+ int_res_sig <= '1'; -- izklopi integrator
+ delay_cycles <= 0;
+
+ end if; --start pogoj
+
+ end if;--clk pogoj
+
+
+ end process;
+
+end generate; --konec MODE_3
+
+
+
+end Behavioral;
Index: izolirana_perfuzija_udov/Red Pitaya/FPGA/BRAM_buffer.vhd
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/FPGA/BRAM_buffer.vhd (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/FPGA/BRAM_buffer.vhd (revision 336)
@@ -0,0 +1,138 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13.10.2018 11:54:07
+-- Design Name:
+-- Module Name: BRAM_buffer - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity BRAM_buffer is
+ generic (
+ bit_num : natural := 10; --number of data bits
+ buffer_size : natural := 26); -- buffer size in bits, 5 bit gets 32 different values
+
+ port (
+ clk: in std_logic;
+
+ AD_wr_en: in std_logic; --from AD unit, enable writing into bram
+ AD_addr: in unsigned ( (buffer_size - 1) downto 0); --from AD unit, address for writing
+ PE_addr: in unsigned ( (buffer_size - 1) downto 0 ); -- from PE_unit, address for reading
+ PE_wr_en: in std_logic; -- from PE_unit, enable writing into PE unit
+ data_in : in unsigned ( (bit_num - 1) downto 0 ); --data from ADC
+ data_out : out unsigned ( (bit_num - 1) downto 0 ); -- data for PE_unit
+ BUFF_data_ready: out std_logic --signal, ki PE_enoti pove, da so podatki pripravljeni (prviè)--preveri ali je to potrebno, ker bodo itak samo nièle letele iz PE enote predn se kaj vpiše, nièle lahko na raèunalniku preè vržem
+ );
+
+end BRAM_buffer;
+
+architecture Behavioral of BRAM_buffer is
+
+---- COMPONENTS ----
+
+ component single_port_bram is
+
+ generic (
+ bit_num : natural := 10; --number of data bits
+ buffer_size : natural := 5); -- buffer size in bits, 5 bit gets 32 different values
+
+ port (
+ clk: in std_logic;
+ bram_en: in std_logic;
+ wr_en: in std_logic;
+ addr: in unsigned ( (buffer_size - 1) downto 0 );
+ data_in : in unsigned ( (bit_num - 1) downto 0 ); --data from ADC
+ data_out : out unsigned ( (bit_num - 1) downto 0 ) -- data for PE_unit
+ );
+
+ end component;
+
+
+---- SIGNALS ----
+
+ signal addr_sig: unsigned ( (buffer_size - 1) downto 0);
+ signal bram_en_sig: std_logic;
+
+ signal zeros: unsigned ( (buffer_size - 1) downto 0 ) := (others => '0');
+
+ type state_type is (WRITE, READ, IDLE); -- definicija stanj
+ signal state: state_type;
+
+
+begin
+
+--------------------COMBINATIONAL PART-------------------------------------
+ state <= WRITE when AD_wr_en = '1' else --stanja
+ READ when PE_wr_en = '1' else
+ IDLE when (AD_wr_en = '0' and PE_wr_en = '0');
+
+
+ addr_sig <= AD_addr when state = WRITE else
+ PE_addr when state = READ else--mux to choose addresses for writing or reading
+ zeros when state = IDLE;
+
+
+ bram_en_sig <= AD_wr_en or PE_wr_en; -- bram enable signal
+
+
+ --------------------------------CONNECT UNITS --------------------------------
+ BRAM_connect: single_port_bram generic map (bit_num => bit_num,
+ buffer_size => buffer_size)
+
+ port map (clk => clk,
+ bram_en => bram_en_sig,
+ wr_en => AD_wr_en,
+ addr => addr_sig,
+ data_in => data_in,
+ data_out => data_out);
+
+-------------------SEQUENTIAL PART----------------------------------------------
+
+--- tole je za nastavljanje BUFF_data_ready signala
+ BUFF_data_ready_proc: process (clk)
+ variable BUFF_ON_flag : std_logic := '0';
+
+ begin
+ if ( rising_edge(clk) ) then
+
+ if (AD_addr = 2**buffer_size - 1 and AD_wr_en = '1') then -- pogoj AD_wr_en = '1' zato, da se flag postavi šele ko je izbrana
+ BUFF_ON_flag := '1'; -- konkretno ta enota, drugace se flag postavi takoj, ko addr pride do 2**buffer_size - 1
+ elsif (PE_addr = 2**buffer_size - 1) then -- kar pa je ze, ko se polni prva enota.
+ BUFF_ON_flag := '0';
+ end if;
+
+
+ if (BUFF_ON_flag = '1' ) then
+ BUFF_data_ready <= '1';
+
+ else
+ BUFF_data_ready <= '0';
+ end if;
+
+ end if;
+ end process;
+end Behavioral;
Index: izolirana_perfuzija_udov/Red Pitaya/FPGA/PE_unit.vhd
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/FPGA/PE_unit.vhd (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/FPGA/PE_unit.vhd (revision 336)
@@ -0,0 +1,785 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14.10.2018 11:13:46
+-- Design Name:
+-- Module Name: PE_unit - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PE_unit is
+
+ generic (
+ bit_num : natural := 10; --number of data bits
+ bin_num : natural := 1024; --number of histogram bins
+ buffer_size : natural := 5; -- buffer size in bits, 5 bit gets 32 different values
+ byte: natural := 8;
+ mode: string := "MODE_3" -- modes of operation: MODE_1 = navaden algoritm, MODE_2 = odklop bufferja in 1 enota, MODE_3 = novo od 30.11.2018 naprej
+ );
+
+ port (
+ clk: in std_logic;
+ UC_wr_en: in std_logic; --microprocessor tells PE_unit that it read current data and is ready for the next one -- ustavljanje, pošiljaj histogram takrat, ko je procesor ready, ne vsak clk cikel
+ PE_START: in std_logic; --flag that tells PE_unit that BRAM_buffer is full
+ data_in : in unsigned ( (bit_num - 1) downto 0 ); --data for PE unit from BRAM_buffer
+ BUFF_addr: out unsigned ( (buffer_size - 1) downto 0 ); -- address for BRAM_buffer, goes to PE_addr
+ PE_wr_rd_en: out std_logic; -- signal to tell BRAM_buffer to start sending when '1' and to tell PE_unit to start sending when '0'
+ data_out: out unsigned ( buffer_size downto 0 ); -- output data
+ UC_rd_en_final: out std_logic; --tells microprocessor that whole histogram data is ready to be sent from PE_unit to microprocessor
+ UC_rd_en_current: out std_logic; -- signal, ki procesorju omogoci sprotno branje iz brama2
+ ---MODE_3 additional ports---
+ write_A_M3: in std_logic; --gre na write_A, ko smo v postopku branja,
+ ADC_unit_RESET: out std_logic;
+ PE_RESET: in std_logic
+ );
+end PE_unit;
+
+architecture Behavioral of PE_unit is
+
+---------------------COMPONENTS-----------------------
+ component dual_port_bram is
+
+ generic (
+ bit_num : natural := 10;
+ bin_num : natural := 1024; --number of histogram bins
+ buffer_size : natural := 5 -- buffer size in bits, 5 bit gets 32 different values
+
+ );
+
+ port (
+ -- A side --
+ clk_A: in std_logic;
+ bram_en_A: in std_logic;
+ wr_en_A: in std_logic;
+ addr_A: in unsigned ( (bit_num - 1) downto 0 );
+ data_in_A: in unsigned ( buffer_size downto 0 );
+ data_out_A: out unsigned ( buffer_size downto 0 );
+
+ -- B side --
+ clk_B: in std_logic;
+ bram_en_B: in std_logic;
+ wr_en_B: in std_logic;
+ addr_B: in unsigned ( (bit_num - 1) downto 0 );
+ data_in_B: in unsigned ( buffer_size downto 0 );
+ data_out_B: out unsigned ( buffer_size downto 0 )
+ );
+
+ end component;
+
+
+
+------------------SIGNALS-----------------------------
+
+ signal zeros : unsigned( buffer_size downto 0 ) := (others => '0'); --zero signal
+ signal zeros10: unsigned( (bit_num - 1) downto 0 ) := (others => '0');
+
+ signal old_value : unsigned ( (bit_num - 1) downto 0 );
+ signal new_value : unsigned ( (bit_num - 1) downto 0 );
+
+ signal BUFF_addr_sig : unsigned ( (buffer_size - 1) downto 0 ) := zeros(buffer_size - 1 downto 0); -- address for BRAM_buffer, goes to PE_addr
+
+ type state_type is (IDLE, WRITE, READ, RESET); --definicija avtomata s stirimi stanji
+ signal state: state_type := IDLE;
+
+--values to be writen/read to/from bram1--
+ signal counter_new : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
+ signal counter_in : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
+ signal count_update : std_logic := '0';
+ signal start_counting : std_logic := '0';
+ signal bin_idx : unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
+ --signal bin_idx_reset : unsigned ( (bit_num - 1) downto 0 ) := (others => '0'); --this signal is address to write 0 into bram (to reset bram)
+
+--bram1 control signals--
+ signal addr_A_sig : unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
+ signal addr_B_sig : unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
+ signal data_in_A_sig : unsigned ( buffer_size downto 0 ) := (others => '0');
+ signal data_out_B_sig : unsigned ( buffer_size downto 0 ) := (others => '0');
+
+
+ signal write_A: std_logic := '0';
+ signal read_B: std_logic := '0';
+
+
+--other control signals --
+ signal PE_wr_rd_en_sig: std_logic := '0';
+ signal UC_rd_en_final_sig : std_logic := '0';
+ signal UC_rd_en_current_sig : std_logic := '0';
+ signal UC_wr_en_sig : std_logic := '0';
+ signal UC_wr_en_prev_sig: std_logic := '0';
+
+signal delay_flag : boolean := FALSE; --used only to delay certain signals or states for 1 clock cycle
+
+--MODE_3 signals--
+signal RESET_sig: std_logic := '0'; --gledam rising edge reset signala, zato tudi reset_sig_prev signal
+signal RESET_sig_prev: std_logic := '0';
+signal ADC_unit_RESET_sig: std_logic := '0';
+signal counter : unsigned ( (buffer_size ) downto 0 ) := (others =>'0'); --steje stevilo prejetih podatkov, ko pride do konca je buffer full
+--bram2 signals
+signal write_A_all_modes: std_logic := '0'; --izhod iz multiplekserja; ko sta MODE 1 in 2, je to stari write_A, drugace pa pulzni signal iz ADC_enote v MODE_3
+signal write_A_prev_M3: std_logic := '0'; -- signal, s katerim gledam rising edge write_A_all_modes signala v MODE_3
+signal data_out_bram1_sig : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
+signal data_out_bram2_sig : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
+signal read_B2: std_logic := '0';
+signal addr_B2_sig : unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
+
+
+ signal data_out_sig : unsigned ( (buffer_size ) downto 0 ) := (others => '0');
+
+
+------------------FUNCTIONS-----------------------
+ function check_signal_edge( sig_in: std_logic;
+ sig_in_prev: std_logic;
+ type_of_edge: string) return boolean is --falling or rising
+
+ begin
+
+ if (type_of_edge = "rising") then
+
+ if (sig_in = '1' and sig_in_prev = '0') then
+ return TRUE;
+ else
+ return FALSE;
+ end if;
+
+ elsif (type_of_edge = "falling") then
+
+ if (sig_in = '0' and sig_in_prev = '1') then
+ return TRUE;
+ else
+ return FALSE;
+ end if;
+
+ end if;
+
+ end function;
+
+
+ ----------------------------------------------------------------------------
+
+
+
+
+
+
+
+begin
+
+ BRAM_connect: dual_port_bram generic map (bit_num => bit_num,
+ bin_num => bin_num,
+ buffer_size => buffer_size)
+
+ port map (clk_A => clk,
+ bram_en_A => write_A_all_modes, --spremenjeno 2.12.2018
+ wr_en_A => write_A_all_modes, -- -||-
+ addr_A => addr_A_sig,
+ data_in_A => data_in_A_sig,
+ data_out_A => open,
+
+ clk_B => clk,
+ bram_en_B => read_B,
+ wr_en_B => '0', --ni pisanja v B port, to more biti vedno onemogoèeno
+ addr_B => addr_B_sig,
+ data_in_B => zeros, --open ne pusti, zato sem dal zeros
+ data_out_B => data_out_B_sig );
+
+
+ -------------------------------------NALOGA BRAM_1-----------------------------------------------------
+
+ --stran A: a1) vpisovanje vrednosti iz BRAM_bufferja (preko algoritma za histogram) (state = WRITE)
+ -- a2) vpisovanje nicel (reset pomnilnika) (state = READ)
+
+ --stran B: b1) branje novega counterja (counter_new) za histogram algoritem (state = WRITE)
+ -- b2) branje izhodnih podatkov data_out (state = READ)
+
+ --HKRATI: a1) in b1)
+ -- a2) in b2)
+
+
+
+ ------------------------------ COMB. DEL, KI VELJA ZA VSE MODE-e ------------------------------------------------------------
+
+ BUFF_addr <= BUFF_addr_sig;
+ PE_wr_rd_en <= PE_wr_rd_en_sig;
+ ADC_unit_RESET <= ADC_unit_RESET_sig;
+
+ new_value <= data_in when state = WRITE else
+ (others => '0');-- when state = READ or state = IDLE or state = RESET;
+
+ data_out <= data_out_sig;
+
+ --signals from/to microprocessor
+ UC_rd_en_final <= UC_rd_en_final_sig;
+ UC_rd_en_current <= UC_rd_en_current_sig;
+ UC_wr_en_sig <= UC_wr_en;
+ RESET_sig <= PE_RESET;
+
+
+
+--------------------------------------------------------------------------------------------------------------------------------
+
+
+
+
+--------------------------------MODE_1 AND MODE_2 ------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------------------------------------
+
+MODE_1_MODE_2: if (mode = "MODE_1" or mode = "MODE_2") generate
+
+
+----------------------- COMBINATIONAL PART -----------------
+
+
+
+---- Counter Adder----
+
+ counter_in <= (0 => '1', others => '0') when count_update = '0' else --mux - : tale enka tukaj zato, da ni 'X' na zacetku pr signalih, glej sliko v mapi slike, grafi itd.
+ (counter_new + 1) when count_update = '1'; --important part: this is where counter_new is increased every iteration
+
+
+ counter_new <= data_out_B_sig when state = WRITE else --demux
+ zeros;
+
+
+ ----Data IN/OUT----
+
+ data_in_A_sig <= counter_in when state = WRITE else --mux
+ zeros when state = READ;
+ --TODO: dodaj se za RESET stanje (nicle)
+
+
+ data_out_sig <= data_out_B_sig when state = READ else -- demux
+ zeros;
+
+
+
+ ---- Enable signals ----
+
+ write_A_all_modes <= write_A;
+
+ read_B <= PE_wr_rd_en_sig when state = WRITE else
+ not PE_wr_rd_en_sig when state = READ else
+ '0' when state = IDLE;
+
+
+
+
+---- Address signals ----
+ addr_A_sig <= old_value when state = WRITE else
+ bin_idx - 1 when state = READ and bin_idx > 0 else
+ to_unsigned(bin_num - 1,10) when state = READ and delay_flag = TRUE else -- tukaj naj bo address 1023, da se vpise 0 na to mesto (reset)
+ zeros10 when state = IDLE;
+
+
+ addr_B_sig <= new_value when state = WRITE else
+ bin_idx when state = READ else
+ zeros10 when state = IDLE;
+
+
+
+
+
+
+ ----------------------------------SEQUENTIAL PART -------------------------------------------
+
+
+ ALGORITHM: process(clk)
+
+ variable first_data: std_logic := '0';
+
+
+
+ begin
+
+ if rising_edge(clk) then
+
+ case state is
+
+ when IDLE =>
+
+ write_A <= '0'; -- this one is here, because we have to set it to '0' after program returns from READ state
+ --UC_rd_en_sig <= '0'; --ta tukej zato, da se v hist_system_top vpisejo vse vrednosti na data_out, pol pa sele tale dol pade
+
+ --writing condition--
+ if (PE_START = '1' and UC_rd_en_final_sig = '0' ) then -- and "konec posiljanja flag je ON" ) then -- sem pripravljen na sprejemanje
+
+ if(delay_flag = FALSE) then
+ delay_flag <= TRUE;
+ PE_wr_rd_en_sig <= '1'; --zacni sprejemanje
+ old_value <= zeros10;
+ BUFF_addr_sig <= zeros(buffer_size - 1 downto 0);
+
+ else
+ state <= WRITE;
+ delay_flag <= FALSE; -- ponastavitev delay flaga, da se lahko uporabi se drugje
+ old_value <= new_value;
+ BUFF_addr_sig <= BUFF_addr_sig + 1;
+ --first_data := '0'; --ponastavi, drugace se branje OK izvede samo prvic.
+ end if;
+
+ --reading condition, part 1 ---
+ elsif (PE_START = '0' and PE_wr_rd_en_sig = '1') then --sem pripravljen na pošiljanje -- tole se lahko zgodi sele, ko gre najprej WRITE faza skozi,
+ PE_wr_rd_en_sig <= '0'; -- to pa zato, da od zacetka ne posilja nicel, ampak se vrti v IDLE stanju.
+
+ state <= READ;
+
+
+ --idle condition-----
+ else
+ state <= IDLE;
+ end if;
+
+
+
+
+ when WRITE =>
+
+ if (first_data = '0') then
+ first_data := '1';
+ old_value <= new_value;
+ BUFF_addr_sig <= BUFF_addr_sig + 1;
+
+ write_A <= '1';
+ start_counting <= '1';
+
+ else
+
+ if (write_A = '1') then
+ count_update <= '1';
+ else
+ count_update <= '0';
+ end if;
+
+
+ if (PE_START = '1') then
+ BUFF_addr_sig <= BUFF_addr_sig + 1;
+
+ elsif (PE_START = '0') then
+ BUFF_addr_sig <= (others =>'0'); --zeros(buffer_size - 1 downto 0);
+ delay_flag <= TRUE; -- s tem za en urin cikel zamaknem prehod v IDLE state in ponastavitev vsega, zato da se vsi podatki poracunajo
+ end if;
+
+
+ old_value <= new_value;
+
+
+
+ if (delay_flag = TRUE) then
+ delay_flag <= FALSE;
+ write_A <= '0';
+ count_update <= '0';
+ start_counting <= '0';
+ state <= IDLE;
+ first_data := '0'; --ponastavi, drugace se branje OK izvede samo prvic.
+
+ end if;
+
+
+ end if;
+
+
+
+
+ when READ => --za dodajanje procesorskega signala: signal vpliva samo na poveèevanje indeksov, ne na write in read in brama. samo ob pravem èasu more index poveèat
+ if (bin_idx = to_unsigned(2,bit_num) ) then --tole zato, da mi prvega podatka takoj ne pobriše, oz. da na 0, ampak ga šele potem, ko pride drugi podatek na izhodno vodilo : TODO: A NE BI MOGL BIT 1?? SPODEJ MAM 1 IN PROV DELA
+ write_A <= '1';
+ end if;
+
+
+ UC_rd_en_final_sig <= '1';
+
+ UC_wr_en_prev_sig <= UC_wr_en_sig; --ta signal zato, da lahko gledam falling edge od UC_wr_en, ker na falling edge menjam podatke: novo 15.11.2018
+ -------------------------------------------------------------
+ if (UC_wr_en_sig = '0' and UC_wr_en_prev_sig = '1') then -- ta pogoj je enak, kot da bi rekel if falling_edge (UC_wr_en)
+ bin_idx <= bin_idx + 1;
+ else
+ bin_idx <= bin_idx;
+ end if;
+
+ ------------------------------------------------------------
+ if (bin_idx = bin_num - 1) then
+ --write_A <= '0';
+ bin_idx <= (others =>'0'); --zeros & "0000";
+ delay_flag <= TRUE;
+
+ end if;
+
+ if (delay_flag = TRUE) then
+ delay_flag <= FALSE;
+ state <= IDLE; --menjava stanj mora biti zakasnjena za 1 clk, da se se 1023 podatek vpise na data_out
+ UC_rd_en_final_sig <= '0';
+ end if;
+
+
+ end case;
+
+ end if;
+
+ end process;
+
+end generate;
+--------------------------------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------------------------------------
+
+
+
+
+
+
+
+-----------------------------MODE_3---------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------------------------------------
+MODE_3: if (mode = "MODE_3") generate
+
+
+--priklucitev dodatnega bufferja
+
+ BRAM_2_connect: dual_port_bram generic map (bit_num => bit_num,
+ bin_num => bin_num,
+ buffer_size => buffer_size)
+
+ port map (clk_A => clk,
+ bram_en_A => write_A_all_modes, --spremenjeno 2.12.2018
+ wr_en_A => write_A_all_modes, -- -||-
+ addr_A => addr_A_sig,
+ data_in_A => data_in_A_sig,
+ data_out_A => open,
+
+ clk_B => clk,
+ bram_en_B => read_B2,
+ wr_en_B => '0', --ni pisanja v B port, to more biti vedno onemogoèeno
+ addr_B => addr_B2_sig,
+ data_in_B => zeros,
+ data_out_B => data_out_bram2_sig );
+
+--------COMBINATIONAL PART------------------
+
+---- Counter Adder, BRAM_1----
+
+ counter_in <= (0 => '1', others => '0') when count_update = '0' else --mux - : tale enka tukaj zato, da ni 'X' na zacetku pr signalih, ker counter_new rab, da ga bram inicializira glej sliko v mapi slike, grafi itd.
+ (counter_new + 1) when count_update = '1'; --important part: this is where counter_new is increased every iteration
+
+
+
+ ----Data IN/OUT, BRAM_1----
+
+ data_in_A_sig <= counter_in when state = WRITE else --mux
+ zeros;-- za vsa ostala stanja
+
+
+
+ data_out_bram1_sig <= data_out_B_sig when state = READ else -- demux
+ zeros;
+
+ counter_new <= data_out_B_sig when state = WRITE else --demux
+ zeros;
+
+
+
+
+ ---- Enable signals, BRAM_1 ----
+
+ write_A_all_modes <= write_A_M3 when state = WRITE else
+ write_A when state = READ else --tukaj se vpisuejo nicle
+ '0' when state = IDLE else--v idle zdej pomoje lahko zbrises write_A = '0', preveri
+ '1' when state = RESET; --nicle vpisujes cel cajt, zato '1'
+
+ read_B <= PE_wr_rd_en_sig when state = WRITE else --TODO 31.3.2019: ali ni kar vseeno, da je addr_B_sig = '1', ko WR in RD in '0' else. <- ne, ker se pri WR stanju ta signal postavi z 1 clk zamude
+ not PE_wr_rd_en_sig when state = READ else
+ '0'; -- V stanjih IDLE in RESET
+
+ --TODO: 7.4.2019 PE_wr_rd_en_sig bom preimenoval v read_B_en (zaenkrat samo za na shematiko)!!!!!!!
+
+
+
+
+---- Address signals, BRAM_1 ----
+
+ addr_A_sig <= old_value when state = WRITE else -- P2
+ bin_idx - 1 when state = READ and bin_idx > 0 else --P3
+ to_unsigned(bin_num - 1,10) when state = READ and delay_flag = TRUE else -- tukaj naj bo address 1023, da se vpise 0 na to mesto (reset) P4
+ (others =>'0') when state = IDLE else -- P1
+ bin_idx when state = RESET; --P5
+
+
+ addr_B_sig <= new_value when state = WRITE else
+ bin_idx when state = READ else
+ (others => '0'); --za ostali stanji IDLE in RESET
+
+
+
+
+---- Data IN/OUT, BRAM_2 ----
+
+ --input v bram2 je kar data_in_A_sig prikljucen na input komponente bram2
+ --output bram2 je dat_out_bram2_sig , prikljuceno direktno na outB komponente bram2
+
+
+---- Enable signals, BRAM_2 ----
+
+ --write_A_all_modes je tudi write enable signal bram2
+ read_B2 <= PE_wr_rd_en_sig when state = WRITE else
+ '1' when state = IDLE else --zato, da 1023. podatek pobrise iz data_out_bram2_sig
+ '0'; -- v stanjih READ IN RESET
+--TODO: 7.4.2019 PE_wr_rd_en_sig bom preimenoval v read_B_en (zaenkrat samo za na shematiko)!!!!!!!
+
+
+---- Address signals, BRAM_2 ----
+
+ --addr_A_sig : za vpisovanje je enak naslov kot pri bram1
+
+ addr_B2_sig <= bin_idx when state = WRITE else
+ (others => '0'); -- v stanjih READ, IDLE IN RESET
+
+
+
+
+
+--------skupna logika obeh bram-ov---------------------
+ data_out_sig <= data_out_bram2_sig when state = WRITE else
+ data_out_bram1_sig when state = READ else
+ (others => '0'); --pri IDLE in RESET stanju
+
+
+--------SEQUENTIAL PART---------------------
+
+ ALGORITHM_bram_1: process(clk)
+
+ variable first_data: std_logic := '0';
+ variable buffer_full: std_logic := '0'; -- 0 - ni se poln, 1 - bram je poln
+
+ begin
+
+ if rising_edge(clk) then
+
+ case state is
+
+ when IDLE =>
+
+ if (PE_START = '1') then --START SIGNAL
+
+ write_A <= '0'; -- this one is here, because we have to set it to '0' after program returns from READ state
+
+ if (buffer_full = '0' and RESET_sig = '0') then -- ni se cas za posiljanje, se pravi lahko sprejemam --PISANJE V PE ENOTO
+
+
+ PE_wr_rd_en_sig <= '1'; --tole vezano na read_B, zato ga se vedno obdrzim
+ old_value <= (others => '0');
+ state <= WRITE;
+ --old_value <= new_value;
+
+
+ elsif (buffer_full = '1' and RESET_sig = '0') then --BRANJE NA KONCU IZ PE ENOTE
+ --pisi na vodilo na koncu in resetiraj prvi bram, tako kot do sedaj, skratka pojdi v READ stanje
+ bin_idx <= (others => '0'); --ga resetiram, da je 0, ker ga tudi bram 2 uproablja
+ UC_wr_en_prev_sig <= '0'; -- da ga ponastavim, ker drugace mi 0. podatek takoj preklopi v 1., ne caka na falling edge od UC_wr_en_sig
+ state <= READ;
+
+
+ elsif (check_signal_edge(RESET_sig,RESET_sig_prev,"rising")) then
+ state <= RESET;
+ ADC_unit_RESET_sig <= '1';
+
+ end if;
+
+
+
+ elsif (PE_START = '0') then --CE JE START NA '0'
+
+ if (check_signal_edge(RESET_sig,RESET_sig_prev,"rising")) then
+ state <= RESET;
+ bin_idx <= (others => '0');
+ ADC_unit_RESET_sig <= '1';
+
+ else
+ state <= IDLE;
+ end if;
+
+ end if;
+
+ --stimanje reset signala
+ RESET_sig_prev <= RESET_sig;
+ ----------------------------
+
+
+
+
+ when WRITE =>
+
+ -------------------bram_1 handling---------------------
+ old_value <= new_value;
+ count_update <= '1'; --ta tukaj samo zato, da nimam 'X' v simulaciji, glej sliko v mapi slike_grafi itd.
+
+ write_A_prev_M3 <= write_A_all_modes;
+ if (write_A_all_modes = '1' and write_A_prev_M3 = '0') then --rising edge write signala
+ counter <= counter + 1;
+ end if;
+
+
+ if (counter = 2**buffer_size) then --ko sem prejel maksimalno št. podatkov, ki jih lahko buffer shrani TODO: 18.5.2019: PREVERI TUKEJ, CE JE counter_in = 2*buffer_size -1
+ --kok delaya? -- nc ni treba
+ state <= IDLE;
+ buffer_full := '1';
+ PE_wr_rd_en_sig <= '0';
+ count_update <= '0';
+ counter <= (others => '0');
+ end if;
+
+
+
+ -----------------bram_2 handling ----------------------
+ if (counter > 0 and counter < 2**buffer_size) then --ce si ze vpisal vsaj en podatek in se nisi prisel do konca vpisovanja
+ UC_rd_en_current_sig <= '1'; --povej procesorju, da lahko zacne sprotno branje
+
+ elsif (counter = 2**buffer_size) then
+ UC_rd_en_current_sig <= '0'; -- procesor naj konca sprotno branje
+ end if;
+
+
+ UC_wr_en_prev_sig <= UC_wr_en_sig; --ta signal zato, da lahko gledam falling edge od UC_wr_en, ker na falling edge menjam podatke:
+
+ if (UC_rd_en_current_sig = '1') then --ce je omogoceno sprotno branje, lahko podajas podatke na izhod
+ if (check_signal_edge(UC_wr_en_sig, UC_wr_en_prev_sig, "falling")) then -- ta pogoj je enak, kot da bi rekel if falling_edge (UC_wr_en)
+ bin_idx <= bin_idx + 1;
+ else
+ bin_idx <= bin_idx;
+ end if;
+ end if;
+
+
+-- if (bin_idx = bin_num - 1) then
+-- --bin_idx <= (others =>'0'); --zeros & "0000";
+-- delay_flag <= TRUE;
+-- end if;
+
+-- if (delay_flag = TRUE) then
+-- delay_flag <= FALSE;
+-- --UC_wr_en_prev_sig <= '0';
+-- --bin_idx <= (others => '0');
+-- end if;
+
+
+ --------------------RESET handling--------------------------
+ RESET_sig_prev <= RESET_sig;
+ if (check_signal_edge(RESET_sig,RESET_sig_prev,"rising")) then
+ state <= RESET;
+ bin_idx <= (others =>'0');
+ UC_rd_en_current_sig <= '0';
+ ADC_unit_RESET_sig <= '1';
+ end if;
+
+ -----------------STOP SYSTEM handling ------------------------
+ if (PE_START = '0') then
+ state <= IDLE;
+ UC_rd_en_current_sig <= '0';
+ end if;
+
+
+
+ when READ => --za dodajanje procesorskega signala: signal vpliva samo na poveèevanje indeksov, ne na write in read in brama. samo ob pravem èasu more index poveèat
+
+ UC_rd_en_final_sig <= '1';
+ -------------------------------------------------------------
+ UC_wr_en_prev_sig <= UC_wr_en_sig; --ta signal zato, da lahko gledam falling edge od UC_wr_en, ker na falling edge menjam podatke: novo 15.11.2018
+
+ if (UC_rd_en_final_sig = '1') then --to zato, da, ce se ponesreci vrine kaksen UC_wr_en preden skoci UC_rd_en_final na '1', da se nic ne zgodi
+ if ( check_signal_edge(UC_wr_en_sig, UC_wr_en_prev_sig, "falling") ) then -- ta pogoj je enak, kot da bi rekel if falling_edge (UC_wr_en)
+ bin_idx <= bin_idx + 1;
+ else
+ bin_idx <= bin_idx;
+ end if;
+ end if;
+
+ ------------------------------------------------------------
+ if (bin_idx = to_unsigned(1,bit_num) ) then --tole zato, da mi prvega podatka takoj ne pobriše, oz. da na 0, ampak ga šele potem, ko pride drugi podatek na izhodno vodilo
+ write_A <= '1';
+ end if;
+
+
+ if (bin_idx = bin_num - 1) then
+ bin_idx <= (others =>'0');
+ delay_flag <= TRUE;
+
+ end if;
+
+ if (delay_flag = TRUE) then
+ delay_flag <= FALSE;
+ state <= IDLE; --menjava stanj mora biti zakasnjena za 1 clk, da se se 1023 podatek vpise na data_out
+ UC_rd_en_final_sig <= '0';
+ bin_idx <= (others => '0'); --se enkrat na 0, drugace se zaradi delaya spet postavi na 1
+ buffer_full := '0';
+ end if;
+
+
+ --------------------RESET handling--------------------------
+ RESET_sig_prev <= RESET_sig;
+ if (check_signal_edge(RESET_sig,RESET_sig_prev,"rising")) then
+ state <= RESET;
+ bin_idx <= (others => '0');
+ UC_rd_en_final_sig <= '0';
+ ADC_unit_RESET_sig <= '1';
+ end if;
+
+ -----------------STOP SYSTEM handling ------------------------
+ if (PE_START = '0') then
+ state <= IDLE;
+ UC_rd_en_final_sig <= '0'; --ce gres tkole: READ -> IDLE -> RESET, potem je treba tega tuki ugasnt
+ end if;
+
+
+
+
+ when RESET =>
+
+ bin_idx <= bin_idx + 1; --to je naslov, v katerega se v oba bram-a vpisujejo nicle
+
+ if (bin_idx = bin_num - 1) then
+ bin_idx <= (others => '0');
+ state <= IDLE;
+ ADC_unit_RESET_sig <= '0';
+ end if;
+
+ PE_wr_rd_en_sig <= '0';
+ count_update <= '0';
+ counter <= (others => '0');
+ buffer_full := '0';
+
+
+
+ end case;
+
+ end if;
+
+ end process;
+
+
+end generate;
+
+
+end Behavioral;
Index: izolirana_perfuzija_udov/Red Pitaya/FPGA/dual_port_bram.vhd
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/FPGA/dual_port_bram.vhd (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/FPGA/dual_port_bram.vhd (revision 336)
@@ -0,0 +1,97 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12.10.2018 13:26:08
+-- Design Name:
+-- Module Name: dual_port_ram - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity dual_port_bram is
+
+ generic (
+ bit_num : natural := 10;
+ bin_num : natural := 1024; --number of histogram bins
+ buffer_size : natural := 10 -- buffer size in bits, 5 bit gets 32 different values
+ );
+
+ port (
+ -- A side --
+ clk_A: in std_logic;
+ bram_en_A: in std_logic;
+ wr_en_A: in std_logic;
+ addr_A: in unsigned ( (bit_num - 1) downto 0 );
+ data_in_A: in unsigned ( buffer_size downto 0 );
+ data_out_A: out unsigned ( buffer_size downto 0 );
+
+ -- B side --
+ clk_B: in std_logic;
+ bram_en_B: in std_logic;
+ wr_en_B: in std_logic;
+ addr_B: in unsigned ( (bit_num - 1) downto 0 );
+ data_in_B: in unsigned ( buffer_size downto 0 );
+ data_out_B: out unsigned ( buffer_size downto 0 )
+ );
+
+end dual_port_bram;
+
+architecture Behavioral of dual_port_bram is
+
+ type BRAM_ARRAY is array ( 0 to (bin_num - 1) ) of unsigned ( buffer_size downto 0 );
+ shared variable bram: BRAM_ARRAY := (others => (others => '0'));
+
+
+
+
+begin
+
+ A_side: process (clk_A)
+ begin
+ if (rising_edge(clk_A)) then
+ if (bram_en_A = '1') then
+ if (wr_en_A = '1') then
+ bram(to_integer(addr_A)) := data_in_A;
+ end if;
+ data_out_A <= bram(to_integer(addr_A));
+ end if;
+ end if;
+ end process;
+
+
+ B_side: process (clk_B)
+ begin
+ if (rising_edge(clk_B)) then
+ if (bram_en_B = '1') then
+ if (wr_en_B = '1') then
+ bram(to_integer(addr_B)) := data_in_B;
+ end if;
+ data_out_B <= bram(to_integer(addr_B));
+ end if;
+ end if;
+ end process;
+
+end Behavioral;
Index: izolirana_perfuzija_udov/Red Pitaya/FPGA/hist_system_top.vhd
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/FPGA/hist_system_top.vhd (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/FPGA/hist_system_top.vhd (revision 336)
@@ -0,0 +1,459 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 30.10.2018 09:14:15
+-- Design Name:
+-- Module Name: hist_system_top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity hist_system_top is
+
+ generic (
+ adc_bit_num : natural := 14; --input data from ad converter is 14 bit
+ bit_num : natural := 10; -- number of bits for our data (scaled from 14 bit to 10 bit)
+ bin_num : natural := 1024; -- number of bins in histogram. IMPORTANT: this number has to be equal to 2**bit_num.
+ buffer_size: natural := 24; --size of each BRAM_buffer in bits ; 24 bit = MAX, je izhodni signal HISTOGRAM, ki gre v procesor 24-bitni
+ num_of_units: natural := 1; -- number of BRAM_buffer and PE_unit units. IMPORTANT: MAX NUMBER OF UNITS IS 33, otherwise overflow (i think, check this out) !!!!
+ comm_bit_num: natural := 32; -- uporabljeno za komunikacijo s procesorjem
+ mode: string := "MODE_3"; -- modes of operation: MODE_1 = navaden algoritm, MODE_2 = odklop bufferja in 1 enota, MODE_3 = novo od 30.11.2018 naprej
+ byte: natural := 8
+ );
+
+ port (
+ clk: in std_logic; --iz ADC
+ data_in: in unsigned ( (adc_bit_num - 1) downto 0 ); --iz ADC
+ INT_res: out std_logic; --signal za reset integratorja, pride iz ADC_unit, to peles na vezje
+
+ PM_trigger_in: in unsigned ( (adc_bit_num - 1) downto 0);
+ --vhodni/izhodni signali za komunikacijo s procesorjem
+ rstn: in std_logic; --reset signal. Ko je '0' resetira prejete podatke
+ HW_addr: in std_logic_vector ( (comm_bit_num - 1) downto 0 );
+ data_from_UC: in std_logic_vector ( (comm_bit_num - 1) downto 0 );
+ wr_en: in std_logic; --procesor pove komponenti, da bo pisal vanjo
+ rd_en: in std_logic; -- procesor pove komponenti, da bo bral iz nje <-- Q: ali je lahko tole moj UC_wr_en???
+ data_for_UC: out std_logic_vector ( (comm_bit_num - 1) downto 0 );
+ error: out std_logic;
+ ack: out std_logic
+ -----------------------------------------------------------------------
+ --START: in std_logic; --TODO: premakni v komunikacijsko enoto
+ --UC_wr_en: in std_logic; -- procesor pove hist_system_top, da lahko poslje nov podatek procesorjuTODO: za testiranje ta tukaj, drugace v komunikacijski enoti = ren
+ --data_out: out integer; --TODO: spravi ga v komunikacijsko enoto
+ --RESET: in std_logic;
+ --ADC_threshold: in unsigned ( (11 - 1) downto 0 );
+ --ADC_capt_num_of_samples: in unsigned ( (byte - 1) downto 0 )
+
+ );
+
+
+
+
+end hist_system_top;
+
+architecture Behavioral of hist_system_top is
+
+----------------COMPONENTS---------------------------
+
+ component ADC_unit
+
+ generic ( adc_bit_num : natural := 14; --input data from ad converter is 14 bit
+ bit_num : natural := 10; -- number of bits for our data (scaled from 14 bit to 10 bit)
+ num_of_units: natural := 2; -- number of BRAM_buffer and PE_unit units
+ buffer_size: natural := 5; --size of each BRAM_buffer in bits
+ mode: string := "MODE_3"; -- modes of operation: MODE_1 = navaden algoritm, MODE_2 = odklop bufferja in 1 enota, MODE_3 = novo od 30.11.2018 naprej
+ byte: natural := 8
+
+ );
+
+ port ( clk_in: in std_logic;
+ START: in std_logic; -- start the system
+ data_in : in unsigned ( (adc_bit_num - 1) downto 0 ); --data from ADC
+ ADC_unit_feedback: in std_logic;
+ AD_wr_en: out unsigned ( (num_of_units - 1) downto 0 );-- goes to BRAM_buffer, to AD_wr_en signal
+ AD_addr: out unsigned ( (buffer_size - 1) downto 0 ); -- goes to BRAM_buffer, address signal
+ data_out: out unsigned ( (bit_num - 1) downto 0 ); -- goes to data_in of BRAM_buffer
+ --MODE_3--
+ threshold: in unsigned ( (11 - 1) downto 0 );
+ capt_num_of_samples: in unsigned ( (byte - 1) downto 0);
+ INT_res: out std_logic; --reset signal za integrator
+
+ SW_trigger_value: in unsigned(4 downto 0);
+ PM_trigger_in: in unsigned ( (adc_bit_num - 1) downto 0)
+ );
+ end component;
+
+
+ component BRAM_buffer is
+
+ generic (
+ bit_num : natural := 10; --number of data bits
+ buffer_size : natural := 26); -- buffer size in bits, 5 bit gets 32 different values
+
+ port (
+ clk: in std_logic;
+ AD_wr_en: in std_logic; --from AD unit, enable writing into bram
+ AD_addr: in unsigned ( (buffer_size - 1) downto 0); --from AD unit, address for writing
+ PE_addr: in unsigned ( (buffer_size - 1) downto 0 ); -- from PE_unit, address for reading
+ PE_wr_en: in std_logic; -- from PE_unit, enable writing into PE unit
+ data_in : in unsigned ( (bit_num - 1) downto 0 ); --data from ADC
+ data_out : out unsigned ( (bit_num - 1) downto 0 ); -- data for PE_unit
+ BUFF_data_ready: out std_logic --signal, ki PE_enoti pove, da so podatki pripravljeni (prviè)--preveri ali je to potrebno, ker bodo itak samo nièle letele iz PE enote predn se kaj vpiše, nièle lahko na raèunalniku preè vržem
+ );
+
+ end component;
+
+
+ component PE_unit
+ generic (
+ bit_num : natural := 10;
+ bin_num : natural := 1024;
+ buffer_size : natural := 5;
+ byte: natural := 8;
+ mode: string := "MODE_3" );
+ port (
+ clk: in std_logic;
+ UC_wr_en: in std_logic; --microprocessor tells PE_unit that it read current data and is ready for the next one -- ustavljanje, pošiljaj histogram takrat, ko je procesor ready, ne vsak clk cikel
+ PE_START: in std_logic; --flag that tells PE_unit that BRAM_buffer is full
+ data_in : in unsigned ( (bit_num - 1) downto 0 ); --data for PE unit from BRAM_buffer
+ BUFF_addr: out unsigned ( (buffer_size - 1) downto 0 ); -- address for BRAM_buffer, goes to PE_addr
+ PE_wr_rd_en: out std_logic; -- signal to tell BRAM_buffer to start sending when '1' and to tell PE_unit to start sending when '0'
+ data_out: out unsigned ( buffer_size downto 0 ); -- output data
+ UC_rd_en_final: out std_logic; --tells microprocessor that data is ready to be sent from PE_unit to microprocessor
+ ---MODE_3 additional ports---
+ write_A_M3: in std_logic; --gre na write_A, ko smo v postopku branja,
+ PE_RESET: in std_logic;
+ ADC_unit_RESET: out std_logic;
+ UC_rd_en_current: out std_logic
+ );
+ end component;
+
+
+------------------SIGNALS--------------------------
+
+ --ADC_unit signals
+ signal PE_wr_rd_en_all_units: unsigned ( (num_of_units - 1) downto 0 ) := (others => '0'); -- combines all PE_wr_rd signals together
+ signal zeros: unsigned ( (num_of_units - 1) downto 0 ) := (others => '0');
+ signal ones: unsigned ( (num_of_units - 1) downto 0 ) := (others => '1');
+ signal PE_wr_rd_en_sig: std_logic;-- := '0';
+ signal ADC_unit_feedback_sig: std_logic := '0';
+ signal ADC_threshold_sig: unsigned ( 10 downto 0) := (others => '0');
+ signal ADC_capt_num_of_samples_sig: unsigned ( (byte - 1) downto 0 ) := (others => '0');
+ signal ADC_unit_RESET_sig: std_logic := '0';
+
+ signal SW_trigger_value_sig : unsigned (4 downto 0) := (others => '0');
+
+
+ signal AD_wr_en_sig: unsigned ( (num_of_units - 1) downto 0 ) := (others => '0') ;
+ signal AD_addr_sig: unsigned ( (buffer_size - 1) downto 0 ) := (others => '0');
+ signal ADC_data_sig: unsigned ( (bit_num - 1) downto 0 ) := (others => '0');
+
+ --BRAM_buffer_signals
+ type buff_data_connection is array ( 0 to (num_of_units -1) ) of unsigned ( (bit_num - 1) downto 0 );
+ signal BUFF_data_out : buff_data_connection := (others => (others => '0'));
+
+ signal BUFF_en: unsigned ( (num_of_units - 1) downto 0 );
+ signal BUFF_data_in: unsigned ( (bit_num - 1) downto 0 );
+
+ signal BUFF_data_ready_sig: std_logic := '0';
+ signal PE_BUFF_addr_sig_1 : unsigned ( (buffer_size - 1) downto 0):= (others => '0');
+ signal PE_BUFF_addr_sig_2 : unsigned ( (buffer_size - 1) downto 0);
+
+
+ --PE_unit signals
+ type PE_data_connection is array ( 0 to (num_of_units - 1) ) of unsigned (buffer_size downto 0);
+ signal PE_data_out : PE_data_connection := (others => (others => '0'));
+
+ signal PE_en_1: std_logic;
+ signal PE_en_2: std_logic;
+ signal PE_en_3: std_logic;
+ signal PE_data_in_1: buff_data_connection;
+ signal PE_data_in_2: buff_data_connection;
+
+ signal UC_rd_en_all_units : unsigned ( (num_of_units - 1) downto 0 ) := (others => '0'); -- vsi morjo bit 1, da je UC_rd_en = 1
+ signal UC_rd_en_final_sig: std_logic; --procesor gleda ta signal, ko je 1, prenese 1023 podatkov in to je histogram
+ signal UC_rd_en_current_sig: std_logic;
+ signal UC_wr_en_sig : std_logic := '0'; -- komponenta gleda ta signal (kontrolira ga procesor), ko je falling edge, pošlje nov podatek procesorju
+
+
+ --Other signals
+ shared variable PE_data_sum: unsigned (23 downto 0) := (others => '0'); --glej zapiske za razporeditev podatkov na izhodno vodilo (15.11.2018)
+ signal HISTOGRAM: unsigned (23 downto 0) := (others => '0'); --izhodni podatki
+
+
+ --UC communication signals
+ constant HIST_SYS_ADDR: std_logic_vector (19 downto 0) := X"00000"; --naslov mojega hardwarea je 0
+ signal data_for_UC_sig : std_logic_vector ( (comm_bit_num - 1) downto 0 ) := (others => '0');
+ signal START_sig: std_logic := '0';
+ signal RESET_sig: std_logic := '0';
+
+
+
+
+ signal data_in_mappped_sig: unsigned ( (bit_num - 1) downto 0);
+
+
+begin
+
+
+--------COMBINATIONAL PART----------------
+
+ --M5--
+ PE_wr_rd_en_sig <= '0' when PE_wr_rd_en_all_units = zeros else
+ '1' when PE_wr_rd_en_all_units = ones;
+
+ --M6--
+ UC_rd_en_final_sig <= '0' when UC_rd_en_all_units = zeros else
+ '1' when UC_rd_en_all_units = ones;
+
+
+ --M7--
+ PE_en_3 <= PE_en_2 when (MODE = "MODE_1" or MODE = "MODE_2") else
+ START_sig when MODE = "MODE_3";
+
+
+-- ------SIGNALI, KI SO DRUGACE PRIKLOPLJENI NA PROCESOR------------
+-- data_out <= to_integer(HISTOGRAM);
+
+-- UC_wr_en_sig <= UC_wr_en; --TODO: spremenjeno 16.11. -- to ni vec tako, sedaj je signal povezan na komunikacijsko enoto
+
+-- START_sig <= START; -- TODO: to za zdej, potem bo start povezan preko komunikacijske enote --POVEZANO
+
+
+-- RESET_sig <= RESET;
+-- ADC_threshold_sig <= ADC_threshold;
+-- ADC_capt_num_of_samples_sig <= ADC_capt_num_of_samples;
+-----------------------------------------------------------------------------
+
+
+ --Multiplekserji / Demultiplekserji za eliminacijo bufferjev
+ --D1--
+ PE_en_1 <= AD_wr_en_sig(0) when (MODE = "MODE_2" or MODE = "MODE_3") else --ko je samo 1 enota, je itak AD_wr_en samo std_logic, ima samo 0-ti element
+ '0';
+
+ BUFF_en <= AD_wr_en_sig when MODE = "MODE_1" else
+ (others => '0');
+
+ --D2--
+ PE_data_in_1(0) <= ADC_data_sig when (MODE = "MODE_2" or MODE = "MODE_3") else
+ (others => '0');
+
+ BUFF_data_in <= ADC_data_sig when MODE = "MODE_1" else
+ (others => '0');
+
+ --M1--
+ PE_en_2 <= PE_en_1 when (MODE = "MODE_2" or MODE = "MODE_3") else
+ BUFF_data_ready_sig;
+
+ --M2--
+ PE_data_in_2 <= PE_data_in_1 when (MODE = "MODE_2" or MODE = "MODE_3") else
+ BUFF_data_out;
+
+ --M3--
+ PE_BUFF_addr_sig_2 <= (others => '0') when (MODE = "MODE_2" or MODE = "MODE_3") else
+ PE_BUFF_addr_sig_1;
+
+ --M4--
+ ADC_unit_feedback_sig <= UC_rd_en_final_sig when ( MODE = "MODE_2" or (MODE = "MODE_3" and ADC_unit_RESET_sig = '0') ) else
+ '1' when (MODE = "MODE_3" and ADC_unit_RESET_sig = '1') else
+ PE_wr_rd_en_sig;-- za MODE_1
+
+
+
+------------------------CONNECT COMPONENTS---------------------
+
+ ADC_unit_connect: ADC_unit generic map ( adc_bit_num => adc_bit_num,
+ bit_num => bit_num,
+ num_of_units => num_of_units,
+ buffer_size => buffer_size,
+ byte => byte,
+ mode => mode)
+
+ port map (clk_in => clk,
+ START => START_sig,
+ data_in => data_in,
+ ADC_unit_feedback => ADC_unit_feedback_sig,
+ AD_wr_en => AD_wr_en_sig,
+ AD_addr => AD_addr_sig,
+ data_out => ADC_data_sig,
+ threshold => ADC_threshold_sig,
+ capt_num_of_samples => ADC_capt_num_of_samples_sig,
+ INT_res => INT_res,
+
+ SW_trigger_value => SW_trigger_value_sig,
+ PM_trigger_in => PM_trigger_in
+ );
+
+
+
+ BUFF_ON_OFF: if (num_of_units /= 1) generate -- if generate vklaplja in izklaplja BRAM_buffer glede na stevilo enot (num_of_units)
+
+ BRAM_buffer_connect: for i in 0 to (num_of_units - 2) generate
+
+ BUFF: BRAM_buffer generic map ( bit_num => bit_num,
+ buffer_size => buffer_size )
+
+ port map ( clk => clk,
+ AD_wr_en => BUFF_en(i),
+ AD_addr => AD_addr_sig,
+ PE_addr => PE_BUFF_addr_sig_2,
+ PE_wr_en => PE_wr_rd_en_sig,
+ data_in => BUFF_data_in,
+ data_out => buff_data_out(i),
+ BUFF_data_ready => open );
+ end generate;
+
+ BRAM_buffer_connect_BUFF_last: BRAM_buffer generic map ( bit_num => bit_num,
+ buffer_size => buffer_size )
+
+ port map ( clk => clk,
+ AD_wr_en => BUFF_en(num_of_units - 1),
+ AD_addr => AD_addr_sig,
+ PE_addr => PE_BUFF_addr_sig_2,
+ PE_wr_en => PE_wr_rd_en_sig,
+ data_in => BUFF_data_in,
+ data_out => buff_data_out(num_of_units - 1),
+ BUFF_data_ready => BUFF_data_ready_sig ); --zadnji sprozi branje v PE_enoto
+
+ end generate;
+
+
+ PE_unit_connect: for i in 0 to (num_of_units - 1) generate
+
+ PE: PE_unit generic map ( bit_num => bit_num,
+ bin_num => bin_num,
+ buffer_size => buffer_size,
+ byte => byte,
+ mode => mode )
+
+ port map ( clk => clk,
+ PE_START => PE_en_3,
+ data_in => PE_data_in_2(i),
+ BUFF_addr => PE_BUFF_addr_sig_1,
+ PE_wr_rd_en => PE_wr_rd_en_all_units(i),
+ data_out => PE_data_out(i),
+ UC_rd_en_final => UC_rd_en_all_units(i), --komponenta pove procesorju, da je data ready za posiljanje v procesor
+ UC_rd_en_current => UC_rd_en_current_sig,
+ UC_wr_en => UC_wr_en_sig, -- procesor pove komponenti, da lahko poslje nov podatek
+ write_A_M3 => PE_en_1,
+ ADC_unit_RESET => ADC_unit_RESET_sig,
+ PE_RESET => RESET_sig
+ );
+
+ end generate;
+
+
+--------------SEQUENTIAL PART --------------------------------
+
+ HIST_RECONSTRUCTION: process (clk)
+ --variable PE_data_sum: integer := 0; --TODO: stevilo bitov tega signala in izhodnega signala mora biti:
+ begin -- N = buffer_size + log(number_of_units) / log(2)
+
+ if ( rising_edge(clk) ) then
+
+
+ if (UC_rd_en_final_sig = '1') then
+ PE_data_sum := (others => '0'); --da se ponastavi na 0 pred vsakim seštevanjem
+ for i in 0 to (num_of_units - 1) loop
+ PE_data_sum := PE_data_sum + to_integer(PE_data_out(i)); --TODO: ali rabim tukaj to_integer ?? Bo pravilno tudi èe ga ni (signala imata razlicno st. bitov)???
+ end loop;
+
+
+ elsif (UC_rd_en_current_sig = '1') then
+
+ PE_data_sum := (others => '0'); --da se ponastavi na 0 pred vsakim seštevanjem
+
+ for i in 0 to (num_of_units - 1) loop
+ PE_data_sum := PE_data_sum + to_integer(PE_data_out(i)); --TODO: ali rabim tukaj to_integer ?? Bo pravilno tudi èe ga ni (signala imata razlicno st. bitov)???
+ end loop;
+
+ end if;
+
+
+
+ HISTOGRAM <= PE_data_sum;
+
+
+ end if;
+
+ end process;
+
+
+
+ -----------------------COMMUNICATION WITH MICROPROCESSOR-----------------
+
+
+ REC_FROM_MICROPROCESSOR: process (clk)
+
+ begin
+
+ if ( rising_edge(clk) ) then
+
+ if (rstn = '0') then
+ START_sig <= '0';
+ elsif ( wr_en = '1' and HW_addr(19 downto 0) = HIST_SYS_ADDR ) then -- Q: kaksen naj bo HW address?? --mora biti 19 downto 0, tako kot na vajah
+ START_sig <= data_from_UC(0);
+ RESET_sig <= data_from_UC(1);
+ ADC_threshold_sig <= unsigned(data_from_UC(18 downto 8));
+ ADC_capt_num_of_samples_sig <= unsigned(data_from_UC(26 downto 19));
+ SW_trigger_value_sig <= unsigned(data_from_UC(31 downto 27));
+
+ end if;
+
+ end if;
+
+ end process;
+
+ -----------------------
+ UC_wr_en_sig <= rd_en; -- signal za menjavo izhodnih podatkov iz komponente
+ data_for_UC_sig <= std_logic_vector(HISTOGRAM) & "00000" & START_sig & UC_rd_en_current_sig & UC_rd_en_final_sig; --Q: a bo to OK, ta pretvorba?? Se kej podatkov izgubi ali pomesa??
+ error <= '0'; -- iz vaje 7
+
+ --data_for_UC_sig <=== zlozim vse podatke, ki jih hocem poslati procesorju v 32 bitni signal
+
+ SEND_TO_MICROPROCESSOR: process (HW_addr, wr_en, rd_en, UC_rd_en_final_sig)
+
+ begin
+
+ if ( (wr_en or rd_en) = '1' ) then
+ ack <= '1';
+ end if;
+
+ if ( HW_addr(19 downto 0) = HIST_SYS_ADDR ) then
+ data_for_UC <= data_for_UC_sig;
+ else
+ data_for_UC <= (others =>'0');
+ end if;
+
+ end process;
+
+ --Q: kje pa tukaj pride rn_en oz UC_wr_en_sig v postev???
+
+
+
+
+
+end Behavioral;
Index: izolirana_perfuzija_udov/Red Pitaya/FPGA/single_port_bram.vhd
===================================================================
--- izolirana_perfuzija_udov/Red Pitaya/FPGA/single_port_bram.vhd (nonexistent)
+++ izolirana_perfuzija_udov/Red Pitaya/FPGA/single_port_bram.vhd (revision 336)
@@ -0,0 +1,76 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13.10.2018 11:17:24
+-- Design Name:
+-- Module Name: single_port_bram - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity single_port_bram is
+
+ generic (
+ bit_num : natural := 10; --number of data bits
+ buffer_size : natural := 26); -- buffer size in bits, 5 bit gets 32 different values
+
+ port (
+ clk: in std_logic;
+ bram_en: in std_logic;
+ wr_en: in std_logic;
+ addr: in unsigned ( (buffer_size - 1) downto 0 );
+ data_in : in unsigned ( (bit_num - 1) downto 0 ); --data from ADC
+ data_out : out unsigned ( (bit_num - 1) downto 0 ) -- data for PE_unit
+ );
+
+end single_port_bram;
+
+architecture Behavioral of single_port_bram is
+
+
+ type BRAM_ARRAY is array ( 0 to (2**buffer_size - 1) ) of unsigned ( (bit_num - 1) downto 0 ); -- bin_num * bit num array for hist storage
+ signal bram : BRAM_ARRAY := (others => (others => '0'));
+
+
+
+begin
+
+ BRAM_handle: process(clk)
+
+ begin
+
+ if rising_edge(clk) then
+ if (bram_en = '1') then
+ if (wr_en = '1') then
+ bram(to_integer(addr)) <= data_in;
+ end if;
+ data_out <= bram(to_integer(addr));
+ end if;
+ end if;
+ end process;
+
+
+end Behavioral;