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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /cvi/apps/l2d2_easyroc/easiroc.h @ 299

  → /cvi/apps/l2d2_easyroc/easiroc.h @ 298

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 299 → Rev 298

/cvi/apps/l2d2_easyroc/easiroc.h
13,9 → 13,7
#define WRITEDATA_DELAY 40
#define EASIROC_MAX_READ_N_WORDS 100
//------------------------------------------------------------------------------------------------------
int easiroc_Init(const char* SiTCP_MASTER_IP, unsigned int daq_mode) ;
23,8 → 21,6
int WriteData(SOCKET sock, unsigned int data);
int easiroc_LoadIni(const char *iniFile);
void PrepareFPGA();
int DebugFPGA(SOCKET socket);
35,17 → 31,11
int TransmitReadSC(SOCKET socket);
int PreparePSC(int CurrentCh, int CurrentProbeType);
void easiroc_PrintData();
int ADCOneCycle_wHeader_ver2(SOCKET socket, FILE* file, int stopping);
int ADCOneCycle_wHeader_ver2(SOCKET socket, FILE* file);
void ADCStop(SOCKET socket);
int ContinuousADC_ver2(SOCKET socket, char *file_name, int MaxCycleNum);
int easiroc_singleADCstart();
int easiroc_singleADCevent(unsigned int *retData);
int easiroc_singleADCstop();
int easiroc_fTransmitSC();
int easiroc_fTransmitReadSC();
int easiroc_fAsicInitialize();