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| 16 | f9daq | 1 | #ifndef __VIC_H__ |
| 2 | #define __VIC_H__ |
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| 3 | |||
| 4 | //------------------------------------------------------------------------------------------ |
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| 5 | // vic.h - some constants about the VIC68A chip from cypress semiconductor |
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| 6 | // |
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| 7 | // (c) 1999-2004 ARW Elektronik |
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| 8 | // |
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| 9 | // this source code is published under GPL (Open Source). You can use, redistrubute and |
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| 10 | // modify it unless this header is not modified or deleted. No warranty is given that |
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| 11 | // this software will work like expected. |
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| 12 | // This product is not authorized for use as critical component in life support systems |
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| 13 | // wihout the express written approval of ARW Elektronik Germany. |
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| 14 | // |
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| 15 | // Please announce changes and hints to ARW Elektronik |
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| 16 | // |
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| 17 | // |
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| 18 | // $Log: Vic.h,v $ |
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| 19 | // Revision 1.3 2004/07/24 07:07:26 klaus |
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| 20 | // Update copyright to 2004 |
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| 21 | // |
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| 22 | // Revision 1.2 2003/11/15 19:12:51 klaus |
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| 23 | // Update copyright to 2003 |
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| 24 | // |
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| 25 | // Revision 1.1.1.1 2003/11/14 23:16:33 klaus |
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| 26 | // First put into repository |
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| 27 | // |
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| 28 | // Revision 1.3 2002/10/27 16:17:48 klaus |
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| 29 | // Typing bug fixed caused at log addition |
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| 30 | // |
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| 31 | // Revision 1.2 2002/10/27 16:11:03 klaus |
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| 32 | // Added CVS log into header |
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| 33 | // |
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| 34 | // what who when |
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| 35 | // finished first release to use with the PCIVME interface of ARW AR 24.11.1997 |
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| 36 | // SRR corrected from SSR AR 18.04.1999 |
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| 37 | // |
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| 38 | |||
| 39 | /* all address offsets relative to vic base */ |
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| 40 | |||
| 41 | #define VICR1 (WORD)0x07 /* VMEbus Interrupt Control Register #.. */ |
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| 42 | #define VICR2 (WORD)0x0b |
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| 43 | #define VICR3 (WORD)0x0f |
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| 44 | #define VICR4 (WORD)0x13 |
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| 45 | #define VICR5 (WORD)0x17 |
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| 46 | #define VICR6 (WORD)0x1b |
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| 47 | #define VICR7 (WORD)0x1f |
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| 48 | |||
| 49 | #define LICR1 (WORD)0x27 /* Local interrupt control register .. */ |
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| 50 | #define LICR2 (WORD)0x2b |
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| 51 | #define LICR3 (WORD)0x2f |
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| 52 | #define LICR4 (WORD)0x33 |
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| 53 | #define LICR5 (WORD)0x37 |
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| 54 | #define LICR6 (WORD)0x3b |
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| 55 | #define LICR7 (WORD)0x3f |
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| 56 | #define LIVBR (WORD)0x57 /* Local interrupt vector base register */ |
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| 57 | |||
| 58 | #define ICGSICR (WORD)0x43 /* ICGS interrupt control register */ |
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| 59 | #define ICGSVBR (WORD)0x4f /* ICGS vector base register */ |
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| 60 | |||
| 61 | #define ICMSICR (WORD)0x47 /* ICMS interrupt control register */ |
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| 62 | #define ICMSVBR (WORD)0x53 /* ICMS vector base register */ |
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| 63 | |||
| 64 | #define EGICR (WORD)0x4b /* Error group interrupt control register */ |
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| 65 | #define EGIVBR (WORD)0x5b /* Error group interrupt vector base rg */ |
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| 66 | |||
| 67 | #define ICSR (WORD)0x5f /* Interprozessor communication switch rg */ |
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| 68 | #define ICR0 (WORD)0x63 |
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| 69 | #define ICR1 (WORD)0x67 |
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| 70 | #define ICR2 (WORD)0x6b |
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| 71 | #define ICR3 (WORD)0x6f |
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| 72 | #define ICR4 (WORD)0x73 |
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| 73 | #define ICR5 (WORD)0x77 |
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| 74 | #define ICR6 (WORD)0x7b |
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| 75 | #define ICR7 (WORD)0x7f |
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| 76 | |||
| 77 | #define VIICR (WORD)0x03 /* VMEbus Interrupter Interrupt Control */ |
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| 78 | #define VIRSR (WORD)0x83 /* VMEbus interrupt request status reg */ |
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| 79 | #define VIVR1 (WORD)0x87 /* VMEbus interrupt vector register .. */ |
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| 80 | #define VIVR2 (WORD)0x8b |
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| 81 | #define VIVR3 (WORD)0x8f |
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| 82 | #define VIVR4 (WORD)0x93 |
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| 83 | #define VIVR5 (WORD)0x97 |
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| 84 | #define VIVR6 (WORD)0x9b |
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| 85 | #define VIVR7 (WORD)0x9f |
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| 86 | |||
| 87 | #define TTR (WORD)0xa3 /* transfer timeout register */ |
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| 88 | #define LTR (WORD)0xa7 /* local timing register */ |
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| 89 | #define ICR (WORD)0xaf /* interface configuration register */ |
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| 90 | |||
| 91 | #define ARCR (WORD)0xb3 /* arbiter/requester configuration register*/ |
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| 92 | #define AMSR (WORD)0xb7 /* address modifier source register */ |
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| 93 | #define BESR (WORD)0xbb /* bus error source register */ |
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| 94 | |||
| 95 | #define DSICR (WORD)0x23 /* DMA status interrupt control register */ |
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| 96 | #define DSR (WORD)0xbf /* DMA status register */ |
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| 97 | |||
| 98 | #define SSCR00 (WORD)0xc3 /* slave select 0 control register 0 */ |
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| 99 | #define SSCR01 (WORD)0xc7 /* slave select 0 control register 1 */ |
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| 100 | #define SSCR10 (WORD)0xcb /* slave select 1 control register 0 */ |
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| 101 | #define SSCR11 (WORD)0xcf /* slave select 1 control register 1 */ |
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| 102 | |||
| 103 | #define RCR (WORD)0xd3 /* release control register */ |
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| 104 | |||
| 105 | #define BTDR (WORD)0xab /* block transfer definition register */ |
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| 106 | #define BTCR (WORD)0xd7 /* block transfer control register */ |
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| 107 | #define BTLR0 (WORD)0xdb /* block transfer length register 0 */ |
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| 108 | #define BTLR1 (WORD)0xdf /* block transfer length register 1 */ |
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| 109 | |||
| 110 | #define SRR (WORD)0xe3 /* system reset register */ |
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| 111 | |||
| 112 | #endif |
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| 113 | |||
| 114 | //------------------------------------------------------------------------------------------- |
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| 115 | //------------------------------------------------------------------------------------------- |
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| 116 | //------------------------------------------------------------------------------------------- |