Subversion Repositories f9daq

Rev

Rev 17 | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
16 f9daq 1
#ifndef __VIC_H__
2
#define __VIC_H__
3
 
4
//------------------------------------------------------------------------------------------
5
// vic.h - some constants about the VIC68A chip from cypress semiconductor
6
//
7
// (c) 1999-2004 ARW Elektronik
8
//
9
// this source code is published under GPL (Open Source). You can use, redistrubute and 
10
// modify it unless this header   is not modified or deleted. No warranty is given that 
11
// this software will work like expected.
12
// This product is not authorized for use as critical component in life support systems
13
// wihout the express written approval of ARW Elektronik Germany.
14
//
15
// Please announce changes and hints to ARW Elektronik
16
// 
17
//
18
// $Log: Vic.h,v $
19
// Revision 1.3  2004/07/24 07:07:26  klaus
20
// Update copyright to 2004
21
//
22
// Revision 1.2  2003/11/15 19:12:51  klaus
23
// Update copyright to 2003
24
//
25
// Revision 1.1.1.1  2003/11/14 23:16:33  klaus
26
// First put into repository
27
//
28
// Revision 1.3  2002/10/27 16:17:48  klaus
29
// Typing bug fixed caused at log addition
30
//
31
// Revision 1.2  2002/10/27 16:11:03  klaus
32
// Added CVS log into header
33
//
34
// what                                                              who    when
35
// finished first release to use with the PCIVME interface of ARW    AR     24.11.1997
36
// SRR corrected from SSR                                            AR     18.04.1999
37
//
38
 
39
/* all address offsets relative to vic base                               */
40
 
41
#define VICR1   (WORD)0x07      /* VMEbus Interrupt Control Register #..  */
42
#define VICR2   (WORD)0x0b   
43
#define VICR3   (WORD)0x0f   
44
#define VICR4   (WORD)0x13   
45
#define VICR5   (WORD)0x17   
46
#define VICR6   (WORD)0x1b   
47
#define VICR7   (WORD)0x1f
48
 
49
#define LICR1   (WORD)0x27      /* Local interrupt control register ..     */
50
#define LICR2   (WORD)0x2b  
51
#define LICR3   (WORD)0x2f  
52
#define LICR4   (WORD)0x33  
53
#define LICR5   (WORD)0x37  
54
#define LICR6   (WORD)0x3b   
55
#define LICR7   (WORD)0x3f   
56
#define LIVBR   (WORD)0x57     /* Local interrupt vector base register     */
57
 
58
#define ICGSICR (WORD)0x43     /* ICGS interrupt control register          */
59
#define ICGSVBR (WORD)0x4f     /* ICGS vector base register                */
60
 
61
#define ICMSICR (WORD)0x47     /* ICMS interrupt control register          */
62
#define ICMSVBR (WORD)0x53     /* ICMS vector base register                */
63
 
64
#define EGICR   (WORD)0x4b     /* Error group interrupt control register   */
65
#define EGIVBR  (WORD)0x5b     /* Error group interrupt vector base rg     */
66
 
67
#define ICSR    (WORD)0x5f     /* Interprozessor communication switch rg   */
68
#define ICR0    (WORD)0x63 
69
#define ICR1    (WORD)0x67 
70
#define ICR2    (WORD)0x6b
71
#define ICR3    (WORD)0x6f
72
#define ICR4    (WORD)0x73
73
#define ICR5    (WORD)0x77 
74
#define ICR6    (WORD)0x7b 
75
#define ICR7    (WORD)0x7f 
76
 
77
#define VIICR   (WORD)0x03     /* VMEbus Interrupter Interrupt Control   */
78
#define VIRSR   (WORD)0x83     /* VMEbus interrupt request status reg    */
79
#define VIVR1   (WORD)0x87     /* VMEbus interrupt vector register ..    */
80
#define VIVR2   (WORD)0x8b 
81
#define VIVR3   (WORD)0x8f 
82
#define VIVR4   (WORD)0x93 
83
#define VIVR5   (WORD)0x97 
84
#define VIVR6   (WORD)0x9b 
85
#define VIVR7   (WORD)0x9f
86
 
87
#define TTR     (WORD)0xa3     /* transfer timeout register               */
88
#define LTR     (WORD)0xa7     /* local timing register                   */
89
#define ICR     (WORD)0xaf     /* interface configuration register        */
90
 
91
#define ARCR    (WORD)0xb3     /* arbiter/requester configuration register*/
92
#define AMSR    (WORD)0xb7     /* address modifier source register        */
93
#define BESR    (WORD)0xbb     /* bus error source register               */
94
 
95
#define DSICR   (WORD)0x23     /* DMA status interrupt control register   */
96
#define DSR     (WORD)0xbf     /* DMA status register                     */
97
 
98
#define SSCR00  (WORD)0xc3     /* slave select 0 control register 0       */
99
#define SSCR01  (WORD)0xc7     /* slave select 0 control register 1       */
100
#define SSCR10  (WORD)0xcb     /* slave select 1 control register 0       */
101
#define SSCR11  (WORD)0xcf     /* slave select 1 control register 1       */
102
 
103
#define RCR     (WORD)0xd3     /* release control register                */
104
 
105
#define BTDR    (WORD)0xab     /* block transfer definition register      */
106
#define BTCR    (WORD)0xd7     /* block transfer control register         */
107
#define BTLR0   (WORD)0xdb     /* block transfer length register 0        */
108
#define BTLR1   (WORD)0xdf     /* block transfer length register 1        */
109
 
110
#define SRR     (WORD)0xe3     /* system reset register                   */
111
 
112
#endif
113
 
114
//-------------------------------------------------------------------------------------------
115
//-------------------------------------------------------------------------------------------
116
//-------------------------------------------------------------------------------------------