Subversion Repositories f9daq

Rev

Details | Last modification | View Log | RSS feed

Rev Author Line No. Line
12 f9daq 1 
control of the KEK PTS with the Wiener VME controller
2 
 
3 
 
4 
<< PTS module specification >>
5 
 
6 
- Block diagram is shown in ptsblock.ps.gz (ptsblock.obj).
7 
- The standard CPLD logic is assumed below.
8 
 
9 
[clock, NIM in/out selection in the CPLD]
10 
   << CPLD logic >>
11 
   (input)            (output)
12 
   ICLK
13 
   EXTCLK0_ --------> EXT[0]
14 
   EXTCLK1_ --------> EXT[1]
15 
   EXTCLK2_ --------> GCLK[2]
16 
   EXTCLK3_ --------> GCLK[3]
17 
   VOUT[0]            GCLK[0] = PCLK
18 
   VOUT[1]            GCLK[1] = SCLK
19 
   BUSA[0]            CLKOUT[0]
20 
   BUSA[1]            CLKOUT[1]
21 
   (internal)
22 
   VMECLK
23 
 
24 
   - EXT[1:0], VOUT[1:0] are lines between the CPLD and FPGA.
25 
   - BUSA[1:0] are lines connected to the connecter in the front panel.
26 
   - VMECLK is an internal register.
27 
   - CLKOUT[1:0] and GCLK[1:0] can be connected to any
28 
     of input signals and VMECLK. This can be set by
29 
     accessing ADR_CLK.
30 
 
31 
[VME addressed]
32 
   A[31:12] must be selected by dip-switches.
33 
   A[11:0]  is available in the module.
34 
   A[11:0] = 12'b0000xxxxxxxx : reserved by CPLD (see pts_h.v)
35 
             others           : available to FPGA
36 
 
37 
[Direction of BUS A-D]
38 
   output = high(1'b1), input = low(1'b0)
39 
 
40 
[Pin assignment of BUS line]
41 
   Front View
42 
   +---------+
43 
   | GND GND |
44 
   | GND  15 |
45 
   | GND  14 |
46 
     .......
47 
   | GND   1 |
48 
   | GND   0 |
49 
   +---------+
50 
 
51 
 
52 
 
53 
 
54 
 
55 
// pts_h.v
56 
//
57 
// 2000/09/09 ver 1.00  S.Nishida  (for ptscpld ver 1.00)
58 
//
59 
 
60 
/* address */
61 
`define ADR_CSR0    6'b000000
62 
  // D[1]   LEDTEST
63 
  // D[0]   RESET
64 
`define ADR_CLK        6'b000001
65 
  // D[15:12] CLKOUT1
66 
  // D[11:8]  CLKOUT0
67 
  // D[7:4]   SCLK
68 
  // D[3:0]   PCLK
69 
`define ADR_VMECLK    6'b000010
70 
  // D[3]   CLKOUT1
71 
  // D[2]   CLKOUT0
72 
  // D[1]   SCLK
73 
  // D[0]   PCLK
74 
`define ADR_BUSA_REG    6'b000100
75 
`define ADR_BUSA_IN    6'b000101
76 
`define ADR_BUSA_DIR    6'b000110
77 
  // D[1:0] BUSA direction
78 
`define ADR_CFG        6'b010000
79 
`define ADR_CSR1    6'b010001
80 
  // D[8]   DONE
81 
  // D[1]   VCS_
82 
  // D[0]   PROGRAM_
83 
`define ADR_MODE    6'b010010
84 
`define ADR_SYSRESET    6'b111111
85 
  // D[15:0] = 0x0000 is necessaly
86 
 
87 
/* BUSA direction */
88 
`define DIRA_FPGA    2'b00
89 
`define DIRA_IN        2'b10
90 
`define DIRA_OUT    2'b11
91 
 
92 
/* CLK source */
93 
`define CLK_IN        4'b0000
94 
`define CLK_EXT0    4'b0001
95 
`define CLK_EXT1    4'b0010
96 
`define CLK_EXT2    4'b0011
97 
`define CLK_EXT3    4'b0100
98 
`define CLK_VME        4'b0101
99 
`define CLK_VOUT0    4'b0110
100 
`define CLK_VOUT1    4'b0111
101 
`define CLK_BUSA0    4'b1000
102 
`define CLK_BUSA1    4'b1001
103 
 
104 
/* Configuration Mode */
105 
`define SELECTMAP_MODE        3'b010
106 
`define SLAVESERIAL_MODE    3'b011