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Rev | Author | Line No. | Line |
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12 | f9daq | 1 | control of the KEK PTS with the Wiener VME controller |
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3 | |||
4 | << PTS module specification >> |
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5 | |||
6 | - Block diagram is shown in ptsblock.ps.gz (ptsblock.obj). |
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7 | - The standard CPLD logic is assumed below. |
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8 | |||
9 | [clock, NIM in/out selection in the CPLD] |
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10 | << CPLD logic >> |
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11 | (input) (output) |
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12 | ICLK |
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13 | EXTCLK0_ --------> EXT[0] |
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14 | EXTCLK1_ --------> EXT[1] |
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15 | EXTCLK2_ --------> GCLK[2] |
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16 | EXTCLK3_ --------> GCLK[3] |
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17 | VOUT[0] GCLK[0] = PCLK |
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18 | VOUT[1] GCLK[1] = SCLK |
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19 | BUSA[0] CLKOUT[0] |
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20 | BUSA[1] CLKOUT[1] |
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21 | (internal) |
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22 | VMECLK |
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23 | |||
24 | - EXT[1:0], VOUT[1:0] are lines between the CPLD and FPGA. |
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25 | - BUSA[1:0] are lines connected to the connecter in the front panel. |
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26 | - VMECLK is an internal register. |
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27 | - CLKOUT[1:0] and GCLK[1:0] can be connected to any |
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28 | of input signals and VMECLK. This can be set by |
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29 | accessing ADR_CLK. |
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30 | |||
31 | [VME addressed] |
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32 | A[31:12] must be selected by dip-switches. |
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33 | A[11:0] is available in the module. |
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34 | A[11:0] = 12'b0000xxxxxxxx : reserved by CPLD (see pts_h.v) |
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35 | others : available to FPGA |
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36 | |||
37 | [Direction of BUS A-D] |
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38 | output = high(1'b1), input = low(1'b0) |
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39 | |||
40 | [Pin assignment of BUS line] |
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41 | Front View |
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42 | +---------+ |
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43 | | GND GND | |
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44 | | GND 15 | |
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45 | | GND 14 | |
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46 | ....... |
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47 | | GND 1 | |
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48 | | GND 0 | |
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49 | +---------+ |
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50 | |||
51 | |||
52 | |||
53 | |||
54 | |||
55 | // pts_h.v |
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56 | // |
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57 | // 2000/09/09 ver 1.00 S.Nishida (for ptscpld ver 1.00) |
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58 | // |
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59 | |||
60 | /* address */ |
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61 | `define ADR_CSR0 6'b000000 |
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62 | // D[1] LEDTEST |
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63 | // D[0] RESET |
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64 | `define ADR_CLK 6'b000001 |
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65 | // D[15:12] CLKOUT1 |
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66 | // D[11:8] CLKOUT0 |
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67 | // D[7:4] SCLK |
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68 | // D[3:0] PCLK |
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69 | `define ADR_VMECLK 6'b000010 |
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70 | // D[3] CLKOUT1 |
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71 | // D[2] CLKOUT0 |
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72 | // D[1] SCLK |
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73 | // D[0] PCLK |
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74 | `define ADR_BUSA_REG 6'b000100 |
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75 | `define ADR_BUSA_IN 6'b000101 |
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76 | `define ADR_BUSA_DIR 6'b000110 |
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77 | // D[1:0] BUSA direction |
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78 | `define ADR_CFG 6'b010000 |
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79 | `define ADR_CSR1 6'b010001 |
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80 | // D[8] DONE |
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81 | // D[1] VCS_ |
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82 | // D[0] PROGRAM_ |
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83 | `define ADR_MODE 6'b010010 |
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84 | `define ADR_SYSRESET 6'b111111 |
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85 | // D[15:0] = 0x0000 is necessaly |
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86 | |||
87 | /* BUSA direction */ |
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88 | `define DIRA_FPGA 2'b00 |
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89 | `define DIRA_IN 2'b10 |
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90 | `define DIRA_OUT 2'b11 |
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91 | |||
92 | /* CLK source */ |
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93 | `define CLK_IN 4'b0000 |
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94 | `define CLK_EXT0 4'b0001 |
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95 | `define CLK_EXT1 4'b0010 |
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96 | `define CLK_EXT2 4'b0011 |
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97 | `define CLK_EXT3 4'b0100 |
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98 | `define CLK_VME 4'b0101 |
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99 | `define CLK_VOUT0 4'b0110 |
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100 | `define CLK_VOUT1 4'b0111 |
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101 | `define CLK_BUSA0 4'b1000 |
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102 | `define CLK_BUSA1 4'b1001 |
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103 | |||
104 | /* Configuration Mode */ |
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105 | `define SELECTMAP_MODE 3'b010 |
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106 | `define SLAVESERIAL_MODE 3'b011 |