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-- Company: 

-- Engineer: 

-- 

-- Create Date: 13.10.2018 11:17:24

-- Design Name: 

-- Module Name: single_port_bram - Behavioral

-- Project Name: 

-- Target Devices: 

-- Tool Versions: 

-- Description: 

-- 

-- Dependencies: 

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

-- 

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity single_port_bram is

    generic (

              bit_num : natural := 10; --number of data bits

              buffer_size : natural := 26); -- buffer size in bits, 5 bit gets 32 different values 

    port (

           clk: in std_logic;

           bram_en: in std_logic;

           wr_en: in std_logic;

           addr: in unsigned ( (buffer_size - 1) downto 0 );

           data_in : in unsigned ( (bit_num - 1) downto 0 ); --data from ADC

           data_out : out unsigned ( (bit_num - 1) downto 0 ) -- data for PE_unit

          );

end single_port_bram;

architecture Behavioral of single_port_bram is

    type BRAM_ARRAY is array ( 0 to (2**buffer_size - 1)  ) of unsigned ( (bit_num - 1) downto 0 ); -- bin_num * bit num array for hist storage

    signal bram : BRAM_ARRAY := (others => (others => '0'));

begin

    BRAM_handle: process(clk)

    begin

        if rising_edge(clk) then

            if (bram_en = '1') then

                if (wr_en = '1') then

                    bram(to_integer(addr)) <= data_in;

                end if;

                data_out <= bram(to_integer(addr));

            end if;

        end if;

    end process;

end Behavioral;