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336 | f9daq | 1 | ---------------------------------------------------------------------------------- |
2 | -- Company: |
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3 | -- Engineer: |
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4 | -- |
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5 | -- Create Date: 12.10.2018 13:26:08 |
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6 | -- Design Name: |
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7 | -- Module Name: dual_port_ram - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool Versions: |
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11 | -- Description: |
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12 | -- |
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13 | -- Dependencies: |
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14 | -- |
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15 | -- Revision: |
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16 | -- Revision 0.01 - File Created |
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17 | -- Additional Comments: |
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18 | -- |
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19 | ---------------------------------------------------------------------------------- |
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20 | |||
21 | |||
22 | library IEEE; |
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23 | use IEEE.STD_LOGIC_1164.ALL; |
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24 | |||
25 | -- Uncomment the following library declaration if using |
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26 | -- arithmetic functions with Signed or Unsigned values |
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27 | use IEEE.NUMERIC_STD.ALL; |
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28 | |||
29 | -- Uncomment the following library declaration if instantiating |
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30 | -- any Xilinx leaf cells in this code. |
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31 | --library UNISIM; |
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32 | --use UNISIM.VComponents.all; |
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33 | |||
34 | entity dual_port_bram is |
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35 | |||
36 | generic ( |
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37 | bit_num : natural := 10; |
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38 | bin_num : natural := 1024; --number of histogram bins |
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39 | buffer_size : natural := 10 -- buffer size in bits, 5 bit gets 32 different values |
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40 | ); |
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41 | |||
42 | port ( |
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43 | -- A side -- |
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44 | clk_A: in std_logic; |
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45 | bram_en_A: in std_logic; |
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46 | wr_en_A: in std_logic; |
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47 | addr_A: in unsigned ( (bit_num - 1) downto 0 ); |
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48 | data_in_A: in unsigned ( buffer_size downto 0 ); |
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49 | data_out_A: out unsigned ( buffer_size downto 0 ); |
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50 | |||
51 | -- B side -- |
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52 | clk_B: in std_logic; |
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53 | bram_en_B: in std_logic; |
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54 | wr_en_B: in std_logic; |
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55 | addr_B: in unsigned ( (bit_num - 1) downto 0 ); |
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56 | data_in_B: in unsigned ( buffer_size downto 0 ); |
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57 | data_out_B: out unsigned ( buffer_size downto 0 ) |
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58 | ); |
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59 | |||
60 | end dual_port_bram; |
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61 | |||
62 | architecture Behavioral of dual_port_bram is |
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63 | |||
64 | type BRAM_ARRAY is array ( 0 to (bin_num - 1) ) of unsigned ( buffer_size downto 0 ); |
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65 | shared variable bram: BRAM_ARRAY := (others => (others => '0')); |
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66 | |||
67 | |||
68 | |||
69 | |||
70 | begin |
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71 | |||
72 | A_side: process (clk_A) |
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73 | begin |
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74 | if (rising_edge(clk_A)) then |
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75 | if (bram_en_A = '1') then |
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76 | if (wr_en_A = '1') then |
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77 | bram(to_integer(addr_A)) := data_in_A; |
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78 | end if; |
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79 | data_out_A <= bram(to_integer(addr_A)); |
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80 | end if; |
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81 | end if; |
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82 | end process; |
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83 | |||
84 | |||
85 | B_side: process (clk_B) |
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86 | begin |
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87 | if (rising_edge(clk_B)) then |
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88 | if (bram_en_B = '1') then |
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89 | if (wr_en_B = '1') then |
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90 | bram(to_integer(addr_B)) := data_in_B; |
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91 | end if; |
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92 | data_out_B <= bram(to_integer(addr_B)); |
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93 | end if; |
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94 | end if; |
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95 | end process; |
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96 | |||
97 | end Behavioral; |