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336 | f9daq | 1 | ---------------------------------------------------------------------------------- |
2 | -- Company: |
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3 | -- Engineer: |
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4 | -- |
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5 | -- Create Date: 13.10.2018 11:54:07 |
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6 | -- Design Name: |
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7 | -- Module Name: BRAM_buffer - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool Versions: |
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11 | -- Description: |
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12 | -- |
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13 | -- Dependencies: |
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14 | -- |
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15 | -- Revision: |
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16 | -- Revision 0.01 - File Created |
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17 | -- Additional Comments: |
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18 | -- |
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19 | ---------------------------------------------------------------------------------- |
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20 | |||
21 | |||
22 | library IEEE; |
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23 | use IEEE.STD_LOGIC_1164.ALL; |
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24 | |||
25 | -- Uncomment the following library declaration if using |
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26 | -- arithmetic functions with Signed or Unsigned values |
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27 | use IEEE.NUMERIC_STD.ALL; |
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28 | |||
29 | -- Uncomment the following library declaration if instantiating |
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30 | -- any Xilinx leaf cells in this code. |
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31 | --library UNISIM; |
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32 | --use UNISIM.VComponents.all; |
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33 | |||
34 | entity BRAM_buffer is |
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35 | generic ( |
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36 | bit_num : natural := 10; --number of data bits |
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37 | buffer_size : natural := 26); -- buffer size in bits, 5 bit gets 32 different values |
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38 | |||
39 | port ( |
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40 | clk: in std_logic; |
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41 | |||
42 | AD_wr_en: in std_logic; --from AD unit, enable writing into bram |
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43 | AD_addr: in unsigned ( (buffer_size - 1) downto 0); --from AD unit, address for writing |
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44 | PE_addr: in unsigned ( (buffer_size - 1) downto 0 ); -- from PE_unit, address for reading |
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45 | PE_wr_en: in std_logic; -- from PE_unit, enable writing into PE unit |
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46 | data_in : in unsigned ( (bit_num - 1) downto 0 ); --data from ADC |
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47 | data_out : out unsigned ( (bit_num - 1) downto 0 ); -- data for PE_unit |
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48 | BUFF_data_ready: out std_logic --signal, ki PE_enoti pove, da so podatki pripravljeni (prvič)--preveri ali je to potrebno, ker bodo itak samo ničle letele iz PE enote predn se kaj vpiše, ničle lahko na računalniku preč vržem |
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49 | ); |
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50 | |||
51 | end BRAM_buffer; |
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52 | |||
53 | architecture Behavioral of BRAM_buffer is |
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54 | |||
55 | ---- COMPONENTS ---- |
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56 | |||
57 | component single_port_bram is |
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58 | |||
59 | generic ( |
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60 | bit_num : natural := 10; --number of data bits |
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61 | buffer_size : natural := 5); -- buffer size in bits, 5 bit gets 32 different values |
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62 | |||
63 | port ( |
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64 | clk: in std_logic; |
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65 | bram_en: in std_logic; |
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66 | wr_en: in std_logic; |
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67 | addr: in unsigned ( (buffer_size - 1) downto 0 ); |
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68 | data_in : in unsigned ( (bit_num - 1) downto 0 ); --data from ADC |
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69 | data_out : out unsigned ( (bit_num - 1) downto 0 ) -- data for PE_unit |
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70 | ); |
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71 | |||
72 | end component; |
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73 | |||
74 | |||
75 | ---- SIGNALS ---- |
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76 | |||
77 | signal addr_sig: unsigned ( (buffer_size - 1) downto 0); |
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78 | signal bram_en_sig: std_logic; |
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79 | |||
80 | signal zeros: unsigned ( (buffer_size - 1) downto 0 ) := (others => '0'); |
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81 | |||
82 | type state_type is (WRITE, READ, IDLE); -- definicija stanj |
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83 | signal state: state_type; |
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84 | |||
85 | |||
86 | begin |
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87 | |||
88 | --------------------COMBINATIONAL PART------------------------------------- |
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89 | state <= WRITE when AD_wr_en = '1' else --stanja |
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90 | READ when PE_wr_en = '1' else |
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91 | IDLE when (AD_wr_en = '0' and PE_wr_en = '0'); |
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92 | |||
93 | |||
94 | addr_sig <= AD_addr when state = WRITE else |
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95 | PE_addr when state = READ else--mux to choose addresses for writing or reading |
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96 | zeros when state = IDLE; |
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97 | |||
98 | |||
99 | bram_en_sig <= AD_wr_en or PE_wr_en; -- bram enable signal |
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100 | |||
101 | |||
102 | --------------------------------CONNECT UNITS -------------------------------- |
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103 | BRAM_connect: single_port_bram generic map (bit_num => bit_num, |
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104 | buffer_size => buffer_size) |
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105 | |||
106 | port map (clk => clk, |
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107 | bram_en => bram_en_sig, |
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108 | wr_en => AD_wr_en, |
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109 | addr => addr_sig, |
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110 | data_in => data_in, |
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111 | data_out => data_out); |
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112 | |||
113 | -------------------SEQUENTIAL PART---------------------------------------------- |
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114 | |||
115 | --- tole je za nastavljanje BUFF_data_ready signala |
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116 | BUFF_data_ready_proc: process (clk) |
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117 | variable BUFF_ON_flag : std_logic := '0'; |
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118 | |||
119 | begin |
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120 | if ( rising_edge(clk) ) then |
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121 | |||
122 | if (AD_addr = 2**buffer_size - 1 and AD_wr_en = '1') then -- pogoj AD_wr_en = '1' zato, da se flag postavi šele ko je izbrana |
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123 | BUFF_ON_flag := '1'; -- konkretno ta enota, drugace se flag postavi takoj, ko addr pride do 2**buffer_size - 1 |
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124 | elsif (PE_addr = 2**buffer_size - 1) then -- kar pa je ze, ko se polni prva enota. |
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125 | BUFF_ON_flag := '0'; |
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126 | end if; |
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127 | |||
128 | |||
129 | if (BUFF_ON_flag = '1' ) then |
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130 | BUFF_data_ready <= '1'; |
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131 | |||
132 | else |
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133 | BUFF_data_ready <= '0'; |
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134 | end if; |
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135 | |||
136 | end if; |
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137 | end process; |
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138 | end Behavioral; |