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| 9 | f9daq | 1 | #ifndef __VIC_H__ |
| 2 | #define __VIC_H__ |
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| 3 | |||
| 4 | //**************************************************************************** |
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| 5 | // Copyright (C) 2001-2004 ARW Elktronik Germany |
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| 6 | // |
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| 7 | // This program is free software; you can redistribute it and/or modify |
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| 8 | // it under the terms of the GNU General Public License as published by |
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| 9 | // the Free Software Foundation; either version 2 of the License, or |
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| 10 | // (at your option) any later version. |
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| 11 | // |
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| 12 | // This program is distributed in the hope that it will be useful, |
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| 13 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 15 | // GNU General Public License for more details. |
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| 16 | // |
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| 17 | // You should have received a copy of the GNU General Public License |
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| 18 | // along with this program; if not, write to the Free Software |
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| 19 | // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 20 | // |
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| 21 | // This product is not authorized for use as critical component in |
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| 22 | // life support systems without the express written approval of |
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| 23 | // ARW Elektronik Germany. |
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| 24 | // |
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| 25 | // Please announce changes and hints to ARW Elektronik |
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| 26 | // |
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| 27 | // Maintainer(s): Klaus Hitschler (klaus.hitschler@gmx.de) |
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| 28 | //**************************************************************************** |
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| 29 | |||
| 30 | //**************************************************************************** |
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| 31 | // |
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| 32 | // vic.h - all definitions about the VIC68A chip |
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| 33 | // |
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| 34 | // $Log: vic.h,v $ |
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| 35 | // Revision 1.6 2004/08/13 19:23:26 klaus |
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| 36 | // conversion to kernel-version 2.6, released version 3.0 |
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| 37 | // |
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| 38 | // Revision 1.5 2002/10/18 21:56:28 klaus |
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| 39 | // completed functional features, untested |
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| 40 | // |
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| 41 | // Revision 1.4 2002/10/18 21:56:28 klaus |
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| 42 | // completed functional features, untested |
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| 43 | // |
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| 44 | // Revision 1.3 2002/10/10 18:57:46 klaus |
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| 45 | // source beautyfied |
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| 46 | // |
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| 47 | //**************************************************************************** |
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| 48 | |||
| 49 | //**************************************************************************** |
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| 50 | // INCLUDES |
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| 51 | #include <linux/types.h> |
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| 52 | |||
| 53 | //**************************************************************************** |
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| 54 | // DEFINES |
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| 55 | #ifndef __KERNEL__ |
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| 56 | #define u8 __u8 |
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| 57 | #define u16 __u16 |
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| 58 | #define u32 __u32 |
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| 59 | #endif |
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| 60 | |||
| 61 | #define VICR1 (u16)0x07 /* VMEbus Interrupt Control Register #.. */ |
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| 62 | #define VICR2 (u16)0x0b |
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| 63 | #define VICR3 (u16)0x0f |
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| 64 | #define VICR4 (u16)0x13 |
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| 65 | #define VICR5 (u16)0x17 |
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| 66 | #define VICR6 (u16)0x1b |
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| 67 | #define VICR7 (u16)0x1f |
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| 68 | |||
| 69 | #define LICR1 (u16)0x27 /* Local interrupt control register .. */ |
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| 70 | #define LICR2 (u16)0x2b |
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| 71 | #define LICR3 (u16)0x2f |
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| 72 | #define LICR4 (u16)0x33 |
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| 73 | #define LICR5 (u16)0x37 |
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| 74 | #define LICR6 (u16)0x3b |
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| 75 | #define LICR7 (u16)0x3f |
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| 76 | #define LIVBR (u16)0x57 /* Local interrupt vector base register */ |
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| 77 | |||
| 78 | #define ICGSICR (u16)0x43 /* ICGS interrupt control register */ |
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| 79 | #define ICGSVBR (u16)0x4f /* ICGS vector base register */ |
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| 80 | |||
| 81 | #define ICMSICR (u16)0x47 /* ICMS interrupt control register */ |
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| 82 | #define ICMSVBR (u16)0x53 /* ICMS vector base register */ |
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| 83 | |||
| 84 | #define EGICR (u16)0x4b /* Error group interrupt control register */ |
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| 85 | #define EGIVBR (u16)0x5b /* Error group interrupt vector base rg */ |
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| 86 | |||
| 87 | #define ICSR (u16)0x5f /* Interprozessor communication switch rg */ |
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| 88 | #define ICR0 (u16)0x63 |
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| 89 | #define ICR1 (u16)0x67 |
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| 90 | #define ICR2 (u16)0x6b |
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| 91 | #define ICR3 (u16)0x6f |
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| 92 | #define ICR4 (u16)0x73 |
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| 93 | #define ICR5 (u16)0x77 |
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| 94 | #define ICR6 (u16)0x7b |
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| 95 | #define ICR7 (u16)0x7f |
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| 96 | |||
| 97 | #define VIICR (u16)0x03 /* VMEbus Interrupter Interrupt Control */ |
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| 98 | #define VIRSR (u16)0x83 /* VMEbus interrupt request status reg */ |
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| 99 | #define VIVR1 (u16)0x87 /* VMEbus interrupt vector register .. */ |
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| 100 | #define VIVR2 (u16)0x8b |
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| 101 | #define VIVR3 (u16)0x8f |
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| 102 | #define VIVR4 (u16)0x93 |
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| 103 | #define VIVR5 (u16)0x97 |
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| 104 | #define VIVR6 (u16)0x9b |
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| 105 | #define VIVR7 (u16)0x9f |
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| 106 | |||
| 107 | #define TTR (u16)0xa3 /* transfer timeout register */ |
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| 108 | #define LTR (u16)0xa7 /* local timing register */ |
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| 109 | #define ICR (u16)0xaf /* interface configuration register */ |
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| 110 | |||
| 111 | #define ARCR (u16)0xb3 /* arbiter/requester configuration register*/ |
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| 112 | #define AMSR (u16)0xb7 /* address modifier source register */ |
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| 113 | #define BESR (u16)0xbb /* bus error source register */ |
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| 114 | |||
| 115 | #define DSICR (u16)0x23 /* DMA status interrupt control register */ |
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| 116 | #define DSR (u16)0xbf /* DMA status register */ |
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| 117 | |||
| 118 | #define SSCR00 (u16)0xc3 /* slave select 0 control register 0 */ |
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| 119 | #define SSCR01 (u16)0xc7 /* slave select 0 control register 1 */ |
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| 120 | #define SSCR10 (u16)0xcb /* slave select 1 control register 0 */ |
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| 121 | #define SSCR11 (u16)0xcf /* slave select 1 control register 1 */ |
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| 122 | |||
| 123 | #define RCR (u16)0xd3 /* release control register */ |
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| 124 | |||
| 125 | #define BTDR (u16)0xab /* block transfer definition register */ |
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| 126 | #define BTCR (u16)0xd7 /* block transfer control register */ |
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| 127 | #define BTLR0 (u16)0xdb /* block transfer length register 0 */ |
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| 128 | #define BTLR1 (u16)0xdf /* block transfer length register 1 */ |
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| 129 | |||
| 130 | #define SRR (u16)0xe3 /* system reset register */ |
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| 131 | |||
| 132 | |||
| 133 | #endif // __VIC_H__ |
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| 134 | |||
| 135 |