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-- Company: 

-- Engineer: 

-- 

-- Create Date: 13.10.2018 11:54:07

-- Design Name: 

-- Module Name: BRAM_buffer - Behavioral

-- Project Name: 

-- Target Devices: 

-- Tool Versions: 

-- Description: 

-- 

-- Dependencies: 

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

-- 

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity BRAM_buffer is

    generic (

              bit_num : natural := 10; --number of data bits

              buffer_size : natural := 26); -- buffer size in bits, 5 bit gets 32 different values 

    port (

           clk: in std_logic;

           AD_wr_en: in std_logic; --from AD unit, enable writing into bram

           AD_addr: in unsigned ( (buffer_size - 1) downto 0); --from AD unit, address for writing

           PE_addr: in unsigned ( (buffer_size - 1) downto 0 ); -- from PE_unit, address for reading

           PE_wr_en: in std_logic; -- from PE_unit, enable writing into PE unit 

           data_in : in unsigned ( (bit_num - 1) downto 0 ); --data from ADC

           data_out : out unsigned ( (bit_num - 1) downto 0 ); -- data for PE_unit

           BUFF_data_ready: out std_logic --signal, ki PE_enoti pove, da so podatki pripravljeni (prviè)--preveri ali je to potrebno, ker bodo itak samo nièle letele iz PE enote predn se kaj vpiše, nièle lahko na raèunalniku preè vržem

          );

end BRAM_buffer;

architecture Behavioral of BRAM_buffer is

---- COMPONENTS ----

    component single_port_bram is

        generic (

                  bit_num : natural := 10; --number of data bits

                  buffer_size : natural := 5); -- buffer size in bits, 5 bit gets 32 different values 

        port (

               clk: in std_logic;

               bram_en: in std_logic;

               wr_en: in std_logic;

               addr: in unsigned ( (buffer_size - 1) downto 0 );

               data_in : in unsigned ( (bit_num - 1) downto 0 ); --data from ADC

               data_out : out unsigned ( (bit_num - 1) downto 0 ) -- data for PE_unit

              );

    end component;

---- SIGNALS ----

    signal addr_sig: unsigned ( (buffer_size - 1) downto 0);

    signal bram_en_sig: std_logic;

    signal zeros: unsigned ( (buffer_size - 1) downto 0 ) := (others => '0');

    type state_type is (WRITE, READ, IDLE); -- definicija stanj

    signal state: state_type;

begin

--------------------COMBINATIONAL PART-------------------------------------

    state <= WRITE when AD_wr_en = '1' else --stanja 

             READ  when PE_wr_en = '1' else

             IDLE  when (AD_wr_en = '0' and PE_wr_en = '0');

    addr_sig <= AD_addr when state = WRITE else

                PE_addr when state = READ  else--mux to choose addresses for writing or reading

                zeros when state = IDLE;

    bram_en_sig <= AD_wr_en or PE_wr_en; -- bram enable signal

 --------------------------------CONNECT UNITS --------------------------------   

    BRAM_connect: single_port_bram generic map (bit_num     => bit_num,

                                                buffer_size => buffer_size)  

                                   port map (clk => clk,

                                             bram_en => bram_en_sig,

                                             wr_en => AD_wr_en,

                                             addr => addr_sig,

                                             data_in => data_in,

                                             data_out => data_out);

-------------------SEQUENTIAL PART----------------------------------------------

--- tole je za nastavljanje BUFF_data_ready signala 

    BUFF_data_ready_proc: process (clk)

        variable BUFF_ON_flag : std_logic := '0';

    begin

        if ( rising_edge(clk) ) then

            if (AD_addr = 2**buffer_size - 1 and AD_wr_en = '1') then -- pogoj AD_wr_en = '1' zato, da se flag postavi šele ko je izbrana

                BUFF_ON_flag := '1';                                  -- konkretno ta enota, drugace se flag postavi takoj, ko addr pride do 2**buffer_size - 1

            elsif (PE_addr = 2**buffer_size - 1) then                 -- kar pa je ze, ko se polni prva enota. 

                BUFF_ON_flag := '0';

            end if;

            if (BUFF_ON_flag = '1' ) then

                BUFF_data_ready <= '1';

            else

                BUFF_data_ready <= '0';

            end if;

        end if;

    end process;

end Behavioral;