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| Rev | Author | Line No. | Line |
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| 86 | f9daq | 1 | #ifndef __PLX9050_H__ |
| 2 | #define __PLX9050_H__ |
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| 3 | |||
| 4 | //**************************************************************************** |
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| 5 | // Copyright (C) 2000-2004 ARW Elektronik Germany |
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| 6 | // |
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| 7 | // |
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| 8 | // This program is free software; you can redistribute it and/or modify |
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| 9 | // it under the terms of the GNU General Public License as published by |
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| 10 | // the Free Software Foundation; either version 2 of the License, or |
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| 11 | // (at your option) any later version. |
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| 12 | // |
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| 13 | // This program is distributed in the hope that it will be useful, |
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| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 16 | // GNU General Public License for more details. |
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| 17 | // |
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| 18 | // You should have received a copy of the GNU General Public License |
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| 19 | // along with this program; if not, write to the Free Software |
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| 20 | // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 21 | // |
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| 22 | // This product is not authorized for use as critical component in |
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| 23 | // life support systems without the express written approval of |
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| 24 | // ARW Elektronik Germany. |
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| 25 | // |
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| 26 | // Please announce changes and hints to ARW Elektronik |
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| 27 | // |
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| 28 | // Maintainer(s): Klaus Hitschler (klaus.hitschler@gmx.de) |
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| 29 | // |
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| 30 | //**************************************************************************** |
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| 31 | |||
| 32 | //**************************************************************************** |
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| 33 | // |
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| 34 | // plx9050.h - Include header for the PCIbus target |
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| 35 | // interface chip PLX9050 from PLX Technology (www.plxtech.com) |
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| 36 | // |
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| 37 | // $Log: plx9050.h,v $ |
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| 38 | // Revision 1.3 2004/08/12 19:59:19 klaus |
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| 39 | // conversion to kernel-version 2.6, released version 6.0 |
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| 40 | // |
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| 41 | // Revision 1.2 2001/11/20 20:12:50 klaus |
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| 42 | // included new header and CVS log |
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| 43 | // |
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| 44 | // |
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| 45 | // derived from original code from Dirk Muehlenberg and ? Mathes AR 18.02.2000 |
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| 46 | // |
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| 47 | //**************************************************************************** |
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| 48 | |||
| 49 | #include <asm/io.h> |
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| 50 | |||
| 51 | /* |
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| 52 | * defining the offsets from PCI CFG Register Area |
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| 53 | * (PCI registers, only accessible during a configuration 0 cycle) |
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| 54 | */ |
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| 55 | /* 15:0 VendorId | 31:16 DeviceId */ |
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| 56 | #define PLX9050_PCIIDR 0x0 |
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| 57 | |||
| 58 | #define PLX9050_PCICR 0x4 |
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| 59 | #define PLX9050_PCISR 0x6 |
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| 60 | #define PLX9050_PCIREV 0x8 |
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| 61 | #define PLX9050_PCICCR 0xB |
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| 62 | #define PLX9050_PCICLSR 0xC |
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| 63 | #define PLX9050_PCILTR 0xD |
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| 64 | #define PLX9050_PCIHTR 0xE |
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| 65 | #define PLX9050_PCIBISTR 0xF |
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| 66 | /* |
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| 67 | ** PCI Base Address Register |
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| 68 | */ |
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| 69 | #define PLX9050_PCIBAR0 0x10 |
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| 70 | #define PLX9050_PCIBAR1 0x14 |
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| 71 | #define PLX9050_PCIBAR2 0x18 |
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| 72 | #define PLX9050_PCIBAR3 0x1C |
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| 73 | #define PLX9050_PCIBAR4 0x20 |
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| 74 | #define PLX9050_PCIBAR5 0x24 |
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| 75 | |||
| 76 | #define PLX9050_PCICIS 0x28 |
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| 77 | |||
| 78 | /* 15:0 Subsystem VendorId */ |
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| 79 | #define PLX9050_PCISVID 0x2C |
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| 80 | |||
| 81 | #define PLX9050_PCIERBAR 0x30 |
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| 82 | |||
| 83 | /* interrupt line routing */ |
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| 84 | #define PLX9050_PCIILR 0x3C |
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| 85 | /* interrupt pin register */ |
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| 86 | #define PLX9050_PCIIPR 0x3D |
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| 87 | |||
| 88 | #define PLX9050_PCIMGR 0x3E |
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| 89 | #define PLX9050_PCIMLR 0x3F |
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| 90 | |||
| 91 | |||
| 92 | /* |
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| 93 | * defining the offsets from Local Base Address |
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| 94 | * (local configuration registers, accessible by way of i/o- or |
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| 95 | * memory cycle) |
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| 96 | */ |
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| 97 | #define PLX9050_LAS0RR 0x0 |
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| 98 | #define PLX9050_LAS1RR 0x4 |
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| 99 | #define PLX9050_LAS2RR 0x8 |
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| 100 | #define PLX9050_LAS3RR 0xC |
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| 101 | #define PLX9050_EROMRR 0x10 |
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| 102 | |||
| 103 | #define PLX9050_LAS0BA 0x14 |
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| 104 | #define PLX9050_LAS1BA 0x18 |
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| 105 | #define PLX9050_LAS2BA 0x1C |
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| 106 | #define PLX9050_LAS3BA 0x20 |
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| 107 | #define PLX9050_EROMBA 0x24 |
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| 108 | |||
| 109 | /* |
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| 110 | * Local Address Space I Bus Region Descriptor Register |
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| 111 | * Bit |
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| 112 | * 0 : Burst enable |
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| 113 | * 1 : Ready Input Enable |
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| 114 | * 2 : Bterm Input Enable |
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| 115 | * 4:3 : Prefetch Count - 00 no, 01 4 lwords, 10 8 lwords, 11 16 lwords |
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| 116 | * 5 : Prefetch Count Enable |
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| 117 | */ |
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| 118 | #define PLX9050_LAS0BRD 0x28 |
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| 119 | #define PLX9050_LAS1BRD 0x2C |
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| 120 | #define PLX9050_LAS2BRD 0x30 |
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| 121 | #define PLX9050_LAS3BRD 0x34 |
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| 122 | #define PLX9050_EROMBRD 0x38 |
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| 123 | |||
| 124 | #define PLX9050_CS0BASE 0x3C |
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| 125 | #define PLX9050_CS1BASE 0x40 |
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| 126 | #define PLX9050_CS2BASE 0x44 |
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| 127 | #define PLX9050_CS4BASE 0x48 |
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| 128 | |||
| 129 | #define PLX9050_INTCSR 0x4C |
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| 130 | |||
| 131 | #define PLX9050_CNTRL 0x50 |
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| 132 | |||
| 133 | #ifndef L_SETBIT |
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| 134 | #define L_SETBIT(addr, b) writel(readl(addr) | (1<<(b)), addr); |
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| 135 | #define W_SETBIT(addr, b) writew(readw(addr) | (1<<(b)), addr); |
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| 136 | #define B_SETBIT(addr, b) writeb(readb(addr) | (1<<(b)), addr); |
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| 137 | |||
| 138 | #define L_CLRBIT(addr, b) writel(readl(addr) & ~(1<<(b)), addr); |
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| 139 | #define W_CLRBIT(addr, b) writew(readw(addr) & ~(1<<(b)), addr); |
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| 140 | #define B_CLRBIT(addr, b) writeb(readb(addr) & ~(1<<(b)), addr); |
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| 141 | #endif |
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| 142 | |||
| 143 | #define PLX9050_ENABLE_BURST(base, i) L_SETBIT(base+PLX9050_LAS0BRD+i*4, 0) |
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| 144 | #define PLX9050_DISABLE_BURST(base, i) L_CLRBIT(base+PLX9050_LAS0BRD+i*4, 0) |
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| 145 | |||
| 146 | #define PLX9050_SET_PREFETCH0(base, i) writel(readl(base+PLX9050_LAS0BRD+i*4) & ~0x180 , base+PLX9050_LAS0BRD+i*4); |
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| 147 | #define PLX9050_SET_PREFETCH4(base, i) writel(readl(base+PLX9050_LAS0BRD+i*4) & ~0x180 | 0x80, base+PLX9050_LAS0BRD+i*4); |
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| 148 | #define PLX9050_SET_PREFETCH8(base, i) writel(readl(base+PLX9050_LAS0BRD+i*4) & ~0x180 | 0x100, base+PLX9050_LAS0BRD+i*4); |
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| 149 | #define PLX9050_SET_PREFETCH16(base, i) writel(readl(base+PLX9050_LAS0BRD+i*4) | 0x180, base+PLX9050_LAS0BRD+i*4); |
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| 150 | |||
| 151 | #endif /* __PLX9050_H__ */ |